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3 57/'HVLJQIORZ Taktfrequenz Constraints RTL Beschreibung Verilog, VHDL Tech-Lib Synthese & Optimierung Netzliste
4 57/%HVFKUHLEXQJ Kontroll-FSM 'DWHQSIDGXQG.RQWUROO =XVWDQGVPDVFKLQH 'HILQLWLRQDOOHU5HJLVWHU Kontrollsignale Status $Q]DKO 3OD]LHUXQJ din + dout (QDEOH6LJQDOH Datenpfad $EODXIGHU.RQWUROO=XVWDQGVPDVFKLQH )XQNWLRQDOLWlWXQG,PSOHPHQWDWLRQZHUGHQ EHVFKULHEHQ
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5 57/6\QWKHVH Die RTL Synthese optimiert die Logik zwischen zwei Registern. Die Struktur ist durch die RTL Beschreibung vorgegeben.
6 %HLVSLHO0XOWLSOL]LHUHUI U.RPSOH[H=DKOHQ Produkt = ( a + bj ) ( c + dj ) Eingangstiming: a b c d inny RE IM ac - bd ad + bc 8-bit serielle Eingangsdaten 16-bit Ausgangsdaten Annahme: - Multiplikation kann in einer Taktperiode durchgeführt werden, - Multiplikation und Addition benötigen mehr als eine Taktperiode Gesucht: 1. Schnellstes Design (kleinste Latency) 2. Kleinstes Design
7 6FKQHOOVWHV'HVLJQ 9LHU0XOWLSOL]LHUHU (LQ$GGLHUHU (LQ6XEWUDKLHUHU /DWHQF\7DNWH inny a ac b bd - RE RE c ad + IM IM d bc
8 6FKQHOOVWHV'HVLJQ Ressourcen Takte Einlesen Mult1 Mult 2 Mult 3 Mult 4 Sub 1 Add 1 Write 1 Write 2 1 A 2 B 3 C 4 D 5 A C A D C D B D 6 AC-BD AD+BC RE IM 3HULRGH/DWHQF\QV7DNWH QV )OlFKH 5HVVRXUFHQ 0XOWLSOL]LHUHU $GGLHUHU6XEWUDKLHUHU 5HJLVWHUELW 5HJLVWHUELW
9 .OHLQVWHV'HVLJQ (LQ0XOWLSOL]LHUHU (LQHQJHPHLQVDPHQ$GGLHUHU6XEWUDKLHUHU /DWHQF\7DNWH inny a ac b bd RE RE c ad +/- IM IM d bc
10 6FKQHOOVWHV'HVLJQ Ressourcen Takte Einlesen Mult1 Add/Sub 1 Write 1 Write 2 1 A 2 B 3 C 4 D 5 A C 6 A D 7 C D 8 B D 9 AC-BD RE 10 AD+BC IM 3HULRGH/DWHQF\QV7DNWH QV )OlFKH 5HVVRXUFHQ 0XOWLSOL]LHUHU $GGLHUHU6XEWUDKLHUHU 5HJLVWHUELW 5HJLVWHUELW
11 &RGH%HLVSLHO.OHLQVWHV'HVLJQ datapath: process variable m_in1, m_in2: unsigned(7 downto 0); variable m_out, a_out: unsigned(15 downto 0); begin wait until clk event and clk= 1 ; --load data into input registers if le_a = 1 then a <= inny; if le_b = 1 then b <= inny; if le_c = 1 then c <= inny; if le_d = 1 then d <= inny; --mux inputs to multipliers if m_mux1 = 0 then m_in1 := a; else m_in1 := b; if m_mux2 = 0 then m_in2 := c; else m_in2 := d; --do multiplies and load into registers m_out := m_in1 m_in2; if le_ac = 1 then ac <= m_out; if le_ad = 1 then ad <= m_out; if le_bd = 1 then bd <= m_out; if le_bc = 1 then bc <= m_out; --do adds if a_mux = 0 then a_out:=ac bd; else a_out:=ad + bc; --load into output registers if le_re = 1 then re <= a_out; else im <= a_out; end process; state_machine: process(clk, reset) begin if clk event and clk = 1 then if reset = 1 then cur_state <= s0; else cur_state <= next_state; end process; state_machine_outputs: process(cur_state, reset) begin --assign defaults for control signals so we dont get latches le_a <= 0; le_b <= 0; le_c <= 0; le_d <= 0; le_ac <= 0; le_ad <= 0; le_bc <= 0; le_bd <= 0; m_mux1 <= 0; m_mux2 <= 0; le_re <= 0; le_im <= 0; --assign control signals and next_state based on cur_state case cur_state is when s0 => next_state <= s1; le_a <= 1; when s1 => next_state <= s2; le_b <= 1; when s2 => next_state<=s3; le_c <= 1; when s3 => next_state<=s4; le_d <= 1; when s4 => next_state<=s5; m_mux1 <= 0; m_mux2 <= 0; le_ac <= 1; when s5 => next_state<=s6; m_mux1 <= 0; m_mux2 <= 1; le_ad <= 1; when s6 => next_state<=s7; m_mux1 <= 1; m_mux2 <= 0; le_bc <= 1; when s7 => next_state<=s8; m_mux1 <= 1; m_mux2 <= 1; le_bd <= 1; when s8 => next_state<=s9; a_mux <= 0; le_re <= 1; when s9 => next_state<=s0; a_mux <= 1; le_im <= 1; when others => next_state <= s0; end case; end process;
12 %HKDYLRUDO'HVLJQIORZ Taktfrequenz Latency Throughput Behavioral Beschreibung Verilog, VHDL Constraints Behavioral Synthese Taktfrequenz Constraints RTL Beschreibung Verilog, VHDL Tech-Lib Synthese & Optimierung Netzliste
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14 %HKDYLRUDO&RGH%HLVSLHO &RGHI UVFKQHOOVWHVXQGNOHLQVWHV'HVLJQ only: process variable a, b, c, d : unsigned (7 downto 0); begin main: loop a := inny; wait until clk event and clk= 1 ; b := inny; wait until clk event and clk= 1 ; c := inny; wait until clk event and clk= 1 ; d := inny; wait until clk event and clk= 1 ; re <= a c b d; im <= a d + b c; wait until clk event and clk= 1 ; end loop; --main end process; --only
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