From VHDL to FPGA

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1 From VHDL to FPGA #1: VHDL simulation Jason Agron University of Kansas Enno Lübbers University of Paderborn 1

2 Field-Programmable Gate Arrays (FPGAs) Fine-grained reconfigurable hardware Gate-Array: regular structure of logic cells, connected through an interconnection network Configuration stored in SRAM, must be loaded on startup EPROM 2

3 Too much logic, too little time... Modern FPGAs provide lots of logic resources Virtex-5: up to 330,000 logic cells DSP blocks, multipliers, block RAM,... Manual design simply unmanageable 3

4 What is VHDL? VHDL (Very high speed integrated logic Hardware Description Language) Developed in the 1980s and 1990s as a documentation language for (digital) hardware as an alternative to complex manuals Soon logic simulators appeared to simulate (= verify the behaviour) these documents Now mainly used as a design entry language for digital logic synthesizers to generate hardware document = describe simulate = verify synthesize = generate 4

5 Overview VHDL as a modelling language Modules Testbenches VHDL simulation Tools Xilinx ISE ModelSim VHDL synthesis Tool Flow Hardware Spartan-3E development board Tools Xilinx ISE Xilinx impact Project work 5

6 VHDL modules my_module inputs i_a i_b o_c o_d outputs G_MYPARAM A module can have Ports Inputs Outputs Parameters ( generics ) This interface is described by an VHDL entity parameters entity my_module is generic ( G_MYPARAM : integer ); port ( i_a : in std_logic; i_b : in std_logic; o_c : out std_logic; o_d : out std_logic ); end my_module; 6

7 Functional description my_module inputs outputs The function of a module is defined By a VHDL description of the module s behaviour, or By assembling the module from other modules (which is a description of its structure) architecture behavioural of my_module is begin c <= a xor b; d <= a and b; end behavioural; This is done through a VHDL architecture 7

8 VHDL testbenches my_module_tb my_module i_a i_b o_c o_d?! G_MYPARAM To verify a modules operation, we need to Stimulate the module s inputs Let the module process the inputs internally Observe the outputs This is usually done by another VHDL module, the testbench 8

9 Introduction to the Xilinx Toolset: Project Navigator (ISE) Project Setup and Simulation 9

10 What is Project Navigator (ISE)? ISE is a tool that is used for Organizing design files. Running processes to implement a design. Compilation Simulation Synthesis ISE is an integrated development environment (IDE). You can create/edit sources Create tests Configure implementation parameters Optimization levels Synthesis/Simulation tools 10

11 Software IDE IDEs: Hardware vs. Software Sources describe programs and libraries. Testing can be done via debugging/simulation. Usually done by stepping through the code line by line. Compilation results in an executable. Hardware IDE. Sources describe entities and libraries. Blocks with I/O ports. Testing is done via debugging/simulation. Usually done by providing stimulus to input ports, and watching behavior of internal state and output ports. The result of simulation is a waveform and I/O. Compilation (synthesis) results in a bitstream, not an executable. A program for an FPGA. The description of a hardware platform. 11

12 How To Get Started Open up ISE. Create a new ISE project. Select File, New Project Select the proper FPGA target, language, etc. Click Next repetitively, and then click Finish. 12

13 Setting Up the Project Parameters Specify the location and name of the project. Specify the parameters of the project. FPGA target. Synthesis tool. Simulation tool. Etc. 13

14 Add HDL sources to the project. Adding Sources to the Project First, Create a subdirectory within the project for the HDL sources to be placed in (maybe called /src/hdl). Now, add the sources to the project. Select the FPGA within the Sources in Project window. Right click and select Add Source or New source. Add existing sources and new sources as needed. NOTE: Some sources can only be made visible by altering the Sources For: parameter! E.G. testbenches 14

15 An entity cannot be simulated! It has I/O ports What should the simulator do for inputs? It is like simulating a video game console without a game or controller. What Can Be Simulated? A testbench can be simulated! A testbench is a wrapper around an entity. It stimulates the input ports. The testbench itself has no I/O ports. It acts as a driver. It is like simulating a game being played on a video game console. 15

16 Select Behavioral Simulation from the Sources For: menu in the top-left. This allows the user to see: Project testbenches. Project UUTs = Units Under Test. Select the testbench that is to be simulated. The Processes menu should now have a Simulation option. Expand this option and double click on Simulate Behavioral Model. Starting a Simulation 16

17 Simulation Output: Waveform The output of simulation is usually a waveform. A clock-cycle accurate representation of signal behavior in the system. A simulator executes the testbench. Allowing the testbench to drive the UUT. The waveform shows the behavior of signals As input to the UUT. Within the UUT (internal signals). As output from the UUT. 17

18 A testbench must do the following: Instantiate a UUT. Define the component. Instantiate the component. Provide stimulus to the UUT. Input signals Clocks A testbench must not do the following: Must not have any I/O ports. I/O can be done via special print statements (screen I/O and file I/O). These are usually simulator specific. Anatomy of a Testbench 18

19 Anatomy of a Testbench - Clocks Purpose of a clock: Periodic signal used for synchronization. Used as a gating mechanism for storage devices Registers use a clock as a signal to store. On every clock edge store a new value. Edges can be rising, falling, or both. The clock model above is encapsulated in a process Runs in parallel with the rest of the testbench continuously. 19

20 Anatomy of a Testbench - Behavioral Stimulus 20

21 Example: Queue (FIFO) FIFO = First In First Out. Operations: Status: Enqueue (Add to queue) Dequeue (Remove from queue) Empty Full 21

22 Backup slides 22

23 Datentypen VHDL bietet spezielle Datentypen und Operatoren zur Hardwarebeschreibung z.b. std_logic als digitales Signal mit den Zuständen U : nicht initialisiert X : unbekannt 0 : logisch 0 1 : logisch 1 Z : hochohmig W : schwaches Signal (0 oder 1) L : schwaches Signal, wahrscheinlich 0 H : schwaches Signal, wahrscheinlich 1 - : Wert irrelevant (don t care) Skalare Typen Arrays integer, natural, unsigned... std_logic_vector, array of integer... Benutzerdefinierte Datenstrukturen (records) Spezielle Datentypen für die Simulation time 23

24 Entity VHDL-Modelle bestehen aus Modulen, sogenannten Entities ähnlich wie Klassendeklarationen beschreiben Schnittstelle der Module entity half_adder is port ( x : in std_logic; y : in std_logic; s : out std_logic; c : out std_logic ); end half_adder; -- x input -- y input -- sum output -- carry output 24

25 Architecture Die Implementation einer entity wird durch eine architecture definiert: architecture behavioural of half_adder is begin s <= x xor y; c <= x and y; end behavioural; Hier handelt es sich um eine sogenannte Verhaltensbeschreibung 25

26 Strukturbeschreibung Aus zwei Halbaddierern lässt sich ein Volladdierer zusammensetzen: entity full_adder is port ( x : in std_logic; -- x input y : in std_logic; -- y input c_in : in std_logic; -- carry input s : out std_logic; -- sum output c_out : out std_logic -- carry output ); end full_adder; architecture structural of full_adder is begin end structural; signal a, b, c : std_logic; ha1 : half_adder port map (x => x, y => y, s => a, c => b); ha2 : half_adder port map (x => a, y => c_in, s => s, c => c); c_out <= b or c; 26

27 Komplexe Operatoren Zum Addieren zweier Zahlen in Binärdarstellung können mehrere Volladdierer zusammengeschaltet werden VHDL kennt aber auch arithmetische Operatoren s <= a + b; s <= a * b;... Außerdem lassen sich Funktionen definieren, z.b. crc <= crc16(x); Funktionen sind immer rein kombinatorisch 27

28 Prozesse Grundlegendes Konstrukt zur Verhaltensbeschreibung: Register process(clk, reset) 1 input + D Q output begin if reset = 1 then output <= 0 ; elsif rising_edge(clk) then output <= input + 1; end if; clk reset clear end process; Prozesse werden ausgeführt, sobald sich eines der Signale in der sensitivity list ändert Getaktete (synchrone) Logik rising_edge(clk) clk event and clk = 1 28

29 Parallelität In VHDL passiert alles gleichzeitig signal a, b, c, d : std_logic; process(clk) begin input a b c d Signal-Zuweisung if rising_edge(clk) then a <= input; b <= a; c <= b; d <= c; end if; clk Register Register Register Register end process; clk a b c d input(0) input(1) input(2) input(3) input(4) input(5) input(6)... X input(0) input(1) input(2) input(3) input(4) input(5)... X X input(0) input(1) input(2) input(3) input(4)... X X X input(0) input(1) input(2) input(3)... 29

30 Parallelität Signal-Zuweisungen erfolgen nicht-blockierend (parallel) Variablen-Zuweisungen erfolgen blockierend (sequentiell) process(clk) variable a, b, c, d : std_logic; begin end process; Variablen-Zuweisung if rising_edge(clk) then a := input; b := a; c := b; d := c; end if; process(clk) variable a, b, c, d : std_logic; begin end process; if rising_edge(clk) then d := input; end if; außerdem existieren Variablen nur innerhalb eines Prozesses 30

31 Demonstration 31

32 Demonstration reset toplevel clk delaycounter displaycounter bcd2seg 50 MHz disp dp an Dezimalpunkt Zähler auf 7-Segment- Anzeige Daten Chip Select 32

33 bcd2seg.vhd -- $Id$ bcd2seg.vhd: BCD to 7-segment display encoder Converts a BCD-coded signal to seven-segment-display Author : Enno Luebbers <enno.luebbers@upb.de> -- Created: Major changes: Enno Luebbers File created. -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.NUMERIC_STD.ALL; entity bcd2seg is port ( i_bcd : in integer range 0 to 15; o_7seg : out std_logic_vector(6 downto 0) ); end bcd2seg; architecture behavioral of bcd2seg is -- A F B -- G E C -- D type slv_array is array(0 to 15) of std_logic_vector(6 downto 0); constant conversiontable : slv_array := ( -- ABCDEFG " ", -- 0 " ", -- 1 " ", -- 2 " ", -- 3 " ", -- 4 " ", -- 5 " ", -- 6 " ", -- 7 " ", -- 8 " ", -- 9 " ", -- A " ", -- B " ", -- C " ", -- D " ", -- E " " -- F ); begin end Behavioral; o_7seg <= conversiontable(i_bcd); 33

34 counter.vhd -- $Id$ counter.vhd: Counter / Generics example Provides a simple up/down counter. Parameters can -- be set through generics Author : Enno Luebbers <enno.luebbers@upb.de> -- Created: Major changes: Enno Luebbers File created. -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter is generic ( G_MAX : natural := 15; -- maximum range G_INIT : natural := 15; -- initial value G_UP : boolean := true -- count up? ); port ( i_clk : in std_logic; i_reset : in std_logic; i_enable : in std_logic; o_value : out natural range 0 to G_MAX ); architecture Behavioral of counter is begin signal value : natural range 0 to G_MAX; -- check generics assert G_MAX >= G_INIT report "G_INIT greater G_MAX" severity FAILURE; count : process(i_clk, i_reset) begin if i_reset = '1' then value <= G_INIT; elsif rising_edge(i_clk) and i_enable = '1' then if G_UP then value <= value + 1; else value <= value - 1; end if; end if; end process; o_value <= value; end Behavioral; end counter; 34

35 toplevel.vhd -- $Id$ toplevel.vhd: VHDL tutorial top level entity Top level entity for Digilent Spartan-3 evaluation board Author : Enno Luebbers <enno.luebbers@upb.de> -- Created: Major changes: Enno Luebbers File created. -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity toplevel is port ( component counter generic ( G_MAX : natural := 15; -- maximum range G_INIT : natural := 15; -- initial value G_UP : boolean := true -- count up? ); port ( i_clk : in std_logic; i_reset : in std_logic; i_enable : in std_logic; o_value : out natural range 0 to G_MAX ); end component; constant DELAY_INIT : integer := ; signal counterenable : std_logic; signal countervalue : integer range 0 to 15 := 0; signal delay : integer range 0 to DELAY_INIT-1 := DELAY_INIT-1; signal displaydata : std_logic_vector(6 downto 0); ); end toplevel; clk : in std_logic; reset : in std_logic; -- LED display disp : out std_logic_vector(6 downto 0); dp : out std_logic; an : out std_logic_vector(3 downto 0) architecture structural of toplevel is component bcd2seg port ( i_bcd : in integer range 0 to 15; o_7seg : out std_logic_vector(6 downto 0) ); end component; begin delaycounter : counter generic map ( ) port map ( ); G_MAX => DELAY_INIT-1, G_INIT => DELAY_INIT-1, G_UP => false i_clk => clk, i_reset => reset, i_enable => '1', o_value => delay 35

36 toplevel.vhd displaycounter : counter generic map ( ) port map ( ); encoder : bcd2seg port map ( ); G_MAX => 15, G_INIT => 0, G_UP => true i_clk => clk, i_reset => reset, i_enable => counterenable, o_value => countervalue i_bcd => countervalue, o_7seg => displaydata counterenable <= '1' when delay = 0 else '0'; disp <= NOT displaydata; dp <= '1'; an <= "1010"; -- the LED display is active-low driven end structural; 36

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