HDL Simulation Framework

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1 PPC-System.mhs CoreGen Dateien.xco HDL-Design.vhd /.v SimGen HDL Wrapper Sim-Modelle.vhd /.v Platgen Coregen XST HDL Simulation Framework RAM Map Netzliste Netzliste Netzliste UNISIM NetGen vcom / vlog.bmm.ngc.ngc.ngc Netzlisten Simulations- Framework NGDbuild Constraints.ucf Bibliotheken Tips and Tricks for HDL simulation Netzliste SIMPRIM NetGen.ngd Netzlisten Kommando- Datei vsim MAP post-map Design.ncd Constraints.pcf NetGen SIMPRIM Netzlisten Timing- Information.sdf PAR finales Design.ncd NetGen Dirk Hutter SIMPRIM Netzlisten Timing- Information.sdf

2 Motivation With bigger FPGAs system complexity increases Time spend for simulation and verification also increases Question: How can simulation be handles in an efficient way? Dirk Hutter FPGA CC 2 /20

3 Outlook Simulation basics HDL Simulation Framework Gatel-level simulations Tips and Ticks Dirk Hutter FPGA CC 3 /20

4 Concepts for efficient Simulations Simulation flow Use an automated simulation flow Add automated tests to your simulations Use GUIs only for investigations and debug Start simulations from basic sources Be able to simulate your design at each build step Dirk Hutter FPGA CC 4 /20

5 Concepts for efficient Simulations Testbench and stimuli Simulations should be self checking and end automatically Add pattern generators and checkers to your testbench or design Integrate simulation debug output to your design Prefer language constructs before simulator commands Implement a full system simulation where possible Dirk Hutter FPGA CC 5 /20

6 Modelsim Simulation Flow HDL vcom / vlog HDL files are compiled to libraries For VHDL compile order is bottom up precompiled Libraries sub Libraries work Library items are loaded for simulation using vsim startup commands runtime commands vsim run During simulation runtime commands for manipulations and examinations are available How to automate? Dirk Hutter FPGA CC 6 /20

7 Simulation Framework - Features Makefile based automated flow Ability to define Sources and libraries Out of tree build is supported A single project file defines the whole simulation Back annotation paths for timing simulation Startup and runtime commands or scripts Each simulation is build into its own directory Libraries and framework files are in subdirectory Easy include of stimulus generation and output checking 7 Dirk Hutter FPGA CC /20

8 Simulation Framework Searchdirs Template Generation Project File Initialization Command File Synthesis Project File Project Makefile Refresh Libraries Start Simulation A templates is created from available sources and can be modified Initialization Create needed libraries Compile sources into chosen libraries Create a makefile for each library using vmake and a common makefile for all libraries Create a command file for vsim Refresh effected simulation sources Start the simulator with the given commands Dirk Hutter FPGA CC 8 /20

9 How to use the Framework make template Setup Simulation make sim_xxx Simulate Change Sources make complile_xxx Restart Simulation make template to crate a projectfile template Modify the template to match your simulation needs make sim_xxx to start your simulation Simulate and change sources make compile_xxx to refresh libraries For debug simulations restart the simulation in the GUI (without restarting the GUI) Dirk Hutter FPGA CC 9 /20

10 Project File # Commands [cmd]-do "do../do/wave.do; do../do/run.do" ############################## [lib] TMU # Synthesis files from../.././script/files.txt../.././src/misc/buildstamp.vhd../.././src/top.vhd ############################## # Simulation files from./sim_files.txt../../../common/src/fifo/fifo_dc18.vhd../../../common/sim/src/cy7c1320bv18.vhd # Board-Level Simulation Entities./src/tmu.vhd # Testbench Sources [lib] work./src/tmu_tb.vhd Dirk Hutter FPGA CC 10 /20

11 Gate-level Simulations Behavioral / functional simulations are not sufficient Gate-level and timing simulations get more and more important for FPGAs Examples: Differences between RTL and implemented design due to (unintended) optimizations Incomplete or wrong constraints Static timing analyzer used for implementation won t find runtime problems like BRAM collisions Dirk Hutter FPGA CC 11 /20

12 Xilinx Design Flow Design Entry Design Synthesis Design Implementation Translate Map Place & Route Generate Bitstream Program Device Synthesis (XST) Translates HDL design into a structural netlist of primitives Translate (NGDbuild) Reduces netlists to Xilinx primitives Mapping (MAP) Maps logic to FPGA components, pre placement Place & Route (PAR) Place and route of mapped design Dirk Hutter FPGA CC 12 /20

13 Simulation Points Design Entry Behavioral: Check RTL sources for intended function Design Synthesis Design Implementation Post syn /trans: Check for unintended syntheses results Translate Map Place & Route Generate Bitstream Post PAR Gate-level simulation with partial timing informations (only block delay) Post MAP Gate-level simulation with full timing Program Device information (block and net delay) Dirk Hutter FPGA CC 13 /20

14 Gate-level Simulation for Xilinx FPGAs HDL Xilinx Build File NetGen HDL Netlist vcom / vlog working vsim Library Timing File NetGen transforms files from the design flow into HDL netlists For each component with a keep_hierarchy attribute a separate netlist can be created Timing information are written to a separate SDF file SDF file holds min, max and typ values of timing Dirk Hutter FPGA CC 14 /20

15 Integration to Simulation Framwork PPC-System.mhs CoreGen Dateien.xco HDL-Design.vhd /.v SimGen HDL Wrapper Sim-Modelle.vhd /.v Platgen Coregen XST RAM Map.bmm Netzliste.ngc Netzliste.ngc Netzliste.ngc NetGen UNISIM Netzlisten Simulations- Framework vcom / vlog NGDbuild Bibliotheken Constraints.ucf Netzliste.ngd NetGen SIMPRIM Netzlisten Kommando- Datei vsim MAP post-map Design.ncd Constraints.pcf NetGen SIMPRIM Netzlisten Timing- Information.sdf PAR finales Design.ncd NetGen SIMPRIM Netzlisten Timing- Information.sdf Dirk Hutter FPGA CC 15 /20

16 Tips and Tricks Dirk Hutter FPGA CC 16 /20

17 Hierarchical Signals Often signals from other hierarchy levels are needed Records for debug signal or VHDL packages are often used VHDL-2008: -- hierarchical signal name << signal.tb.uut.o_n : std_logic >> -- signal a two levels above << signal ^.^.a : std_logic >> -- variable in a package pack << : bit >> Can be used in testbenches in Modelsim 10.x Dirk Hutter FPGA CC 17 /20

18 Unimportant Warnings Get rid of unimportant warnings to see crucial ones Arithmetic warnings before reset # Switch off arithmetics warnings set StdArithNoWarnings 1 set NumericStdNoWarnings 1 # Switch on arithmetics warnings after reset when -label enable_stdwarn {rst = '0'} { echo "### Enabling arithmetic warnings" ; set StdArithNoWarnings 0; set NumericStdNoWarnings 0} BRAM collision checks: SIM_COLLISION_CHECK generic in BRAM primitive Dirk Hutter FPGA CC 18 /20

19 Modelsim Breakpoints Breakpoints can be used to steer simulation progress E.g. stopping a simulation onbreak {resume} when {/testbench/done_condition = 1} { if {[examine /testbench/error] = 0} { echo "### SIMULATION PASSED" } if {[examine /testbench/error]!= 0} { echo "### SIMULATION FAILED" } stop if [batch_mode] { quit -f } } run -all Dirk Hutter FPGA CC 19 /20

20 Modelsim Virtual Signals Signals can be combined to virtual signal and buses Virtual types can be defined Useful for signals not available on testbench level and gate-level simulations # create virtual intermediate bus of control signals virtual signal -install /sim_tb_top { (context /sim_tb_top ) ( ddr3_cs_n_fpga(0) & ddr3_ras_n_fpga & ddr3_cas_n_fpga & ddr3_we_n_fpga )} controls # define types for control signals virtual type {{0b1000 DES} {0b0001 REF} {0b0011 ACT} {0b0101 RD} {0b0100 WR} {0b0110 ZQCS} {default OTHER_STATE}} myctrltype # cast controls to myctrltype and save as myctrlstate virtual function {(myctrltype)/sim_tb_top/controls} myctrlstate Dirk Hutter FPGA CC 20 /20

21 Thank You for Your Attention! Contact: Dirk Hutter Prof. Dr. Volker Lindenstruth Lehrstuhl für Architektur von Hochleistungsrechnern Frankfurt Institute for Advanced Studies

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