Digital Systems with Lab ENGIN 241 Lab 4

Transcription

1 Digital Systems with Lab ENGIN 241 Lab 4 Dr. Honggang Zhang Engineering Department University of Massachusetts Boston

2 Lab 4 Objectives Introduce programmable logic CAD (Computer Aided Design) tools for using programmable logic Introduce programming hardware

3 Lab 4 Implement a Hexadecimal to seven segment display decoder Use Active-HDL to specify design Program into a GAL Interfacing with seven segment display

4 Lab 4 You will need to define the functionality of the BCD to 7-segment display decoder. BCD binary coded decimal The Common Anode Display (CAD) all the anode connections of the LED s are joined together to logic 1 and the individual segments are illuminated by connecting the individual Cathode terminals to a LOW, logic 0 signal.

5 Lab 4 You will need to use two 7406 chips to drive the 7-segment display The 7406 has open collector outputs allowing it to drive LEDs and LED displays

6 Lab 4 Decoder inputs: W, X, Y, Z (Binary) Decoder outputs: A-G (Hex) Define a truth table containing 11 columns For each row define which LEDs on the 7- segment display need to be turned ON

7 Truth Table X1 X2 X3 X4 a b c d e f g Keep in mind that the following HEX values could look the same on the 7-segment display: B = 8, D = 0 (make sure to use lower case letters to distinguish between them)

8 Lab 4 Preliminary Work Items 1 to 4 should be submitted to the instructor no later than 5pm on March 1, Determine the truth table for the system show in Figure 1(a). Write down your truth table. 2. Plot the functions (A to G) on K-maps and write down the minimized Boolean equation for each. 3. Generate a VHDL program, define the input and output pins, and enter the equations for the outputs. Compile and simulate your design. Write down your VHDL program, and show a screen capture of your simulation in Active-HDL. 4. Compile your design once you verify the simulated outputs. Submit the JEDEC (.jed) file before the lab begins next week. your JEDEC file to the instructor. 5. Derive chip implementation circuit diagram and a wire list for the final circuit. 6. Wire your circuit in preparation for the lab. Put a picture of your circuit into your prelab-report. (It is ok if the PLD chip has not been programmed yet).

9 Lab 4 Work You will: Burn your GAL22v10 Connect the full circuit Verify your implemented circuit

10 Programmable Logic A family of components that contains arrays of logic elements (AND, OR, INVERT, LATCH, FLIP- FLOP) that may be configured into any logical function that the component supports. Classes of programmable logic devices: ASICs, FPGAs, PLAs, PROMs, PALs, GALs, and complex PLDs. 10

11 Basic architecture of user programmable device Contains a pre-defined general architecture in which a user can program a design into the device using a set of development tools. Normally consists of one or more arrays of AND and OR terms for implementing logic functions. Many also contain combinations of flip-flops and latches which may be used as storage elements for inputs and outputs of a device. 11

12 Programmable Logic Devices (PLD) ROM read only memory Can implement any function Programmable forms PROM, EPROM, EEPROM PLA programmable logic array PAL programmable array logic GAL generic array logic FPGA field programmable gate array

13 PROMs Programmable Read Only Memories. Consists of a fixed number of AND array terms that feeds a programmable OR array. Mainly used for decoding specific input combinations into output functions, such as memory mapping in microprocessor environments. 13

14 PAL -- Programmable Array Logic Implements equations specified as SOP Circuits include arrays of fuses or switches that set sum and product terms

15 PALs -- Programmable Array Logic Consists of programmable AND terms feeding fixed OR terms. All inputs to the array can be ANDed together, but specific AND terms are dedicated to specific OR terms. Most widely used type of user programmable device. Mainly used to replace multiple TTL logic functions commonly referred to as glue logic. 15

16 AC F 1= AC + AB + BC F BC + AF + 2 = 1 ACD PAL

17 PLAs -- Programmable Logic Arrays. Contain both programmable AND and OR terms which allow any AND term to feed any OR term. PLAs probably have the greatest flexibility with regard to logic functionality. They typically have feedback from the OR array back into the AND array which may be used to implement asynchronous state machines. 17

18 Complex PLDs Complex Programmable Logic Devices. Considered very large PALs that have some characteristics of PLAs. The basic architecture is very much like a PAL 18

19 FPGAs -- Field Programmable Gate Arrays Electrically programmable gate array ICs that contain multiple levels of logic. FPGAs feature high gate densities, high performance, a large number of user-definable inputs and outputs, a flexible interconnect scheme, and a gate-array-like design environment. 19

20 Programming Logic Devices They are programmed by either shorting or opening connections within a device array, thus connecting or disconnecting inputs to a gate. Most hardware programmers receive a fuse information file from a software development package in ASCII format. The ASCII file could either be in JEDEC format for PLDs or HEX format for PROMs. A JEDEC file contains fuse connections that are represented by an address followed by a series of 1 s and 0 s where a 1 indicates a disconnected state and a 0 indicates a connected state. A JEDEC file can also contain information that allows the hardware programmer the ability to perform a functional test on the device. 20

21 isplever_classic2_0 We use isplever from Lattice Semiconductor to generate JEDEC files from.vhd files. You can get isplever classic 2.0 base module from To get a license, you just need to create an account and provide your laptop's MAC address. 21

22 The GAL 22v10 Characteristics: 22 input / output signals 48 product terms 10 flip-flops single bit memories

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24 Lab 4 You will need to define the functionality of the BCD to 7-segment display decoder. BCD binary coded decimal The Common Anode Display (CAD) all the anode connections of the LED s are joined together to logic 1 and the individual segments are illuminated by connecting the individual Cathode terminals to a LOW, logic 0 signal.

25 Open collector 7406

26 Most TTL circuits have a similar structure NAND and AND gates use multiple-emitter transistor or multiple diode junction inputs. NOR and OR gates use separate input transistors. The input will be the cathode of a P-N junction A HIGH input will turn off the junction. Only a leakage current is generated. A LOW input turns on the junction. Relatively large current is generated. Most TTL circuits have some type of totem-pole output configuration.

27 The basic TTL logic circuit is the NAND gate. Diode equivalent for Q 1. Basic TTL NAND gate.

28 TTL NAND gate LOW output

29 A TTL output acts as a current sink in the LOW state because it receives current from the input of the gate that it is driving. Transistor Q 4 of the driving gate is on and essentially shorts point X to ground. LOW voltage at X forwardbiases the emitter base junction of Q 1 & current flows back through Q 4.

30 A TTL output acts as a current sink in the LOW state because it receives current from the input of the gate that it is driving. Q 4 is performing a currentsinking action deriving its current from the input current (I IL ) of the load gate. Q 4 is often called the currentsinking transistor or pulldown transistor because it brings the output voltage down to its LOW state.

31 TTL NAND gate HIGH output

32 A TTL output acts as a current source in the HIGH state a small reverse-bias leakage current. Transistor Q 3 is supplying the input current (I IH ) required by Q 1 of the load gate. Q 3 is often called the currentsourcing or pull-up transistor.

33 The first line of TTL ICs was the 54/74 series from Texas Instruments introduced in Manufacturers use the same numbering system. Prefix indicates manufacturer. SN Texas Instruments. DM National Semiconductor. S Signetics. DM7402, SN7402, S7402 perform the same function. Data sheets contain electrical characteristics, switching characteristics, and recommended operating conditions.

34 Typical TTL series characteristics.

35 Fan-out refers to the load drive capability of an IC output A TTL output has a limit on how much current it can sink in the LOW state, or source in the HIGH state. Exceeding these currents will result in output voltage levels outside specified ranges. Determining fan out Add the I IH for all inputs connected to an output. Sum must be less than the output I OH specification. Add the I IL for all inputs connected to an output. Sum must be less than the output I OL specification.

36 TTL outputs modified this way are called open-collector outputs. CMOS outputs modified this way are called open-drain outputs.

37 Wired-AND operation using open-collector gates.

38 7406/7407 are the recommended due to their high I OL and V OH specifications can sink up to 40mA in the LOW state, can handle output voltages up to 30V in the HIGH state is an open-collector, non-inverting buffer with the same voltage and current ratings as a 7406.

39 A common use of open-collector/drain outputs is as a buffer/driver. Logic circuit designed to have a greater output current and/or voltage capability than an ordinary logic circuit. They allow a weaker output circuit to drive a heavy load. Clock rising edge triggerd J-K flip-flop An open-collector buffer/driver drives a highcurrent, high-voltage load.

40 Open-collector outputs are often used to drive indicator LEDs. An open-collector output can be used to drive an LED indicator. An open-drain CMOS output. D-Latch 7405 is an open-drain hex inverter with 25mA current sink capability.