MC74VHCT138A. 3-to-8 Line Decoder

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1 MCHCT8A -to-8 Line Decoder The MCHCT8A is an advanced high speed CMOS to 8 decoder fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. When the device is enabled, three Binary Select inputs ( A) determine which one of the outputs ( Y) will go Low. When enable input E is held Low or either E or E is held High, decoding function is inhibited and all outputs go high. E, E, and E inputs are provided to ease cascade connection and for use as an address decoder for memory systems. The HCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing. to., because they have full. CMOS level output swings. The HCT8A input structures provide protection when voltages between and. are applied, regardless of the supply voltage. The output structures also provide protection when CC =. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc. Features High Speed: t PD =. ns (Typ) at CC =. Low Power Dissipation: I CC = A (Max) at T A = C TTL Compatible Inputs: IL =.8 ; IH =. Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for. to. Operating Range Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds ma ESD Performance: Human Body Model > ; Machine Model > Chip Complexity: FETs or. Equivalent Gates These Devices are Pb Free and are RoHS Compliant SOIC D SUFFIX CASE B TSSOP DT SUFFIX CASE 8F MARKING DIAGRAMS HCT8AG AWLYWW HCT 8A ALYW A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) A A PIN ASSIGNMENT CC Y E Y E Y E Y Y Y 8 Y ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, May, Rev. Publication Order Number: MCHCT8A/D

2 MCHCT8A FUNCTION TABLE LOGIC DIAGRAM Inputs Outputs E E E A A Y Y Y Y Y Y Y X X H X X X H H H H H H H H X H X X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L H = high level (steady state); L = low level (steady state); X = don t care SELECT INPUTS ENABLE INPUTS A A E E E Y Y Y Y Y Y Y ACTIE-LOW OUTPUTS EXPANDED LOGIC DIAGRAM Y Y A Y A Y E E Y Y Y E IEC LOGIC DIAGRAM A A E E E & BIN/OCT EN Y Y Y Y Y Y Y A A E E E & DMUX G Y Y Y Y Y Y Y

3 MCHCT8A MAXIMUM RATINGS Symbol Parameter Î alue Unit CC DC Supply oltage Î. to +. in DC Input oltage Î. to + out DC Output oltage CC = Î. to +. High or Low State. to CC +. I IK Input Diode Current ma I OK Output Diode Current ( OUT < ; OUT > CC ) ± ma I out DC Output Current, per Pin ± ma I CC DC Supply Current, CC and Pins ± ma P D Power Dissipation in Still Air, SOIC Packages TSSOP Package Î mw Î T stg Storage Temperature to + C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating SOIC Packages: mw/ C from to C TSSOP Package:. mw/ C from to C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or CC ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage.. in DC Input oltage. out DC Output oltage CC = High or Low State. CC T A Operating Temperature + C Î Input Rise and Fall Time CC =. ±. ns/ t r, t f The JA of the package is equal to /Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and figure below. DEICE JUNCTION TEMPERATURE ERSUS TIME TO.% BOND FAILURES Junction Temperature C Time, Hours Time, Years 8,,.8,. 8,.,.,.,8. 8,. NORMALIZED FAILURE RATE FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = C TJ = C TJ = C TJ = C TJ = C TJ = 8 C TIME, YEARS Figure. Failure Rate vs. Time Junction Temperature

4 MCHCT8A Î DC ELECTRICAL CHARACTERISTICS CC T A = C T A 8 CÎ T A C SymbolÎ Parameter Test Conditions () Min Typ Max Min Max Min Max Unit IH Î Minimum High Level Input oltage Î IL Î Maximum Low Level Input oltage Î OH Minimum High Level Output Î oltage IN = IH or IL. I OH = A......Î... IN = IH or IL IN = IH or IL Î Î I OH = ma I OH = 8 ma...8. Î OL Maximum Low Level Output Î oltage IN = IH or IL. I OL = A IN = IH or IL IN = IH or IL Î Î I OL = ma.... I OL = 8 ma.... Î I IN Maximum Input Leakage Current IN =. or to. ±. ±. ±. A Î I CC Maximum Quiescent Supply Î Current IN = CC or. Î... A I CCT Î Quiescent Supply Current IN =.... Î. ma Output Leakage Current OUT =.... Î. I OPD Î AC ELECTRICAL CHARACTERISTICS (Input t r = t f =.ns) Î T A = C T A = 8 C Î T A C Symbol Parameter Test Conditions Min Typ Max Min Max Min Max Unit t PLH, Maximum Propagation Delay, Î CC =. ±. C L = pf ns Input A to Y C L = pf CC =. ±. C L = pf C L = pf t PLH, Maximum Propagation Delay, CC =. ±. C L = pf Input E to Y C L = pf ns. CC =. ±. C L = pf C L = pf Î Î t PLH, Maximum Propagation Delay, Input E or E to Y CC =. ±. C L = pf C L = pf..... ns CC =. ±. C L = pf C L = pf C IN Maximum Input Capacitance pf Î C, CC =. C PD Power Dissipation Capacitance (Note ) pf. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C PD CC f in + I CC. C PD is used to determine the no load dynamic power consumption; P D = C PD CC f in + I CC CC. A

5 MCHCT8A SWITCHING WAEFORMS A Y t PLH ALID.. ALID E. OH Y. OL t PLH OH OL Figure. Figure. E or E. t PLH Y. OH OL Figure. TEST POINT DEICE UNDER TEST OUTPUT C L * *Includes all probe and jig capacitance Figure. Test Circuit ORDERING INFORMATION MCHCT8ADRG Device Package Shipping SOIC (Pb Free) Tape & Reel MCHCT8ADTRG TSSOP * Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. *This package is inherently Pb Free.

6 MCHCT8A PACKAGE DIMENSIONS. (.) T. (.) T. (.) T SEATING PLANE L U PIN IDENT. U D S S X L/ C X K REF. (.) M T U S S 8 A G B U TSSOP CASE 8F ISSUE B H J N N J F DETAIL E DETAIL E K K ÇÇÇ ÉÉÉ SECTION N N. (.) M W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 8.. CONTROLLING DIMENSION: MILLIMETER.. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED. (.) PER SIDE.. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED. (.) PER SIDE.. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.8 (.) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A.... B.... C.. D.... F.... G. BSC. BSC H J....8 J.... K.... K.... L. BSC. BSC M 8 8 SOLDERING FOOTPRINT.. PITCH X. X. DIMENSIONS: MILLIMETERS

7 MCHCT8A PACKAGE DIMENSIONS SOIC CASE B ISSUE K A 8 B P 8 PL. (.) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 8.. CONTROLLING DIMENSION: MILLIMETER.. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.. MAXIMUM MOLD PROTRUSION. (.) PER SIDE.. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE. (.) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B.8... C....8 D.... F.... G. BSC. BSC J...8. K.... M P.8... R.... T SEATING PLANE G D PL. (.) M T B S A S K C M R X J F SOLDERING FOOTPRINT 8X. X. X.8. PITCH 8 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Denver, Colorado 8 USA Phone: or 8 8 Toll Free USA/Canada Fax: or 8 8 Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: 8 8 ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MCHCT8A/D