The schematic diagram of the circuit to be used for each measurement is given at the beginning of each section.

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Exercise 3 Digital Circuits 1 - Introduction Goal of the exercise The goals of this exercise are: - verify the behavior of an asynchronous binary counter - build a decade counter from a binary

1 Exercise 3 Digital Circuits 1 - Introduction Goal of the exercise The goals of this exercise are: - verify the behavior of an asynchronous binary counter - build a decade counter from a binary counter - verify the behavior of a simple Digital/Analog converter. Only the first page of the report form is available for this exercise. Add the required sheets using A4 papers, following the outline used for the previous report. Instruments and circuit setup The required circuits must be arranged on the breadboard. This experiments uses logic circuits with steep edge signals; keep connections as straight and short as possible. The instruments required are - a squarewave generator, frequency range at least 10Hz 1MHz; (available on breadboard) - a two-channel oscilloscope (bandwidth at least 60 MHz) - LEDS and 7-segment display to read logic states. The components required are: - Integrated multistage asynchronous counter (CD4040 or CD 4060) - 4 x 2-input NAND gates (74HC00 or 74LS00) - Resistors for the weight network (see 2.3). The schematic diagram of the circuit to be used for each measurement is given at the beginning of each section. Use +5 V power supply voltage. Power supply must be connected and turned ON for proper circuit operation. Circuit operation can be verified using the oscilloscope, or the LEDs, or the 7-segment display. Warning Remember that in CMOS circuits, all inputs must be connected to a well defined logical state! Also remember that the voltage applied to an integrate circuit cannot exceed the supply voltage range (0V to 5 V for the logic circuits used in this experiment). Therefore, always verify the signal generator before connecting it to the circuit. 1

2 2 - Measurements 2.1 Asynchronous Counter Examine the data sheet of CD4040 counter, in order to identify the function of the various inputs. Mount the CD4040 integrated circuit with 5V supply (Vss 0V, Vdd positive voltage supply). Connect the RESET to a proper logical state in order to enable the counting. a) Connect LEDs and a seven-segment display to the first 4 outputs (Q1 Q4). Apply clock from the on-breadboard variable-frequency squarewave generator. Verify the counting sequence on the LEDs and on the display (reduce the clock frequency as required to see the various logic states). The counter follows a binary sequence, while the display can show only decimal numbers. Verify what happens for counter states b) Verify (using the oscilloscope) that, on the outputs, every square wave has a frequency which is the half of the previous one. Raise the clock rate as required, and synchronize the time base of oscilloscope with the lowest frequency signal. c) Verify that the switching delay increases from a Flip-Flop to the next one along the counter chain. In order to execute this step easily, is useful to increase the clock frequency until the clock period becomes comparable with the propagation delay. The delay measurement is more easy between multiple stages (higher delay, more easy measurement, see next point). Verify that an additional capacitance on a FF output increases the delay. d) Measure the delay of a single counter stage (Flip-Flop), by measuring the delay of a rather long FF chain and then divide it by the number of Flip-Flops. Verify that the delay is function of the number of FF between the two measurement points and does not depend on the divider chain position. e) Leave the Clock input unconnected; verify that, in this condition, the input gather noise from the environment (like an antenna): field from the electric network (50 Hz), electric charges from near (not in contact) objects, etc. Connecting a pullup resistor R PU = 10 kω between the clock input and the positive supply, the input potential is fixed by the pull-up resistor, which has a smaller Z than capacitive coupling, and reduce the noise. f) Leaving the pull-up resistor R PU ans in e), apply clock pulses with a switch towards GND. Verify that whenever you operate the switch (or any contact to ground) the counter receives several clock pulses (look at the counter state on the LEDs or the 7-segm display). R PU V AL CK 2

3 2.2 - Decoder For the following exercises, connect the square wave generator to the clock input. The integrated counter follows a binary sequence (0 15 in the 4 LSBs), but can be converted to a decade counter (0 9) using the reset command. a) Using two-input NAND gates create a circuit (decoder) which recognizes the state 1010 (decimal 10, the next state after 9), and use the output to reset the counter. A couple of 2- input NAND gate (left from the 7400 used in the SR FF) allows to build the reset circuit. b) Verify the operation in almost-static condition (slow advancement, outputs state verification through LEDs) and dynamic conditions (fast clock, signal verified on the oscilloscope). The next step is a refinement on decoder and counters. Try it only after completing 2.3. c) Find the circuit to be used to get a counter modulus 13, build it using 2-input NAND gates, and verify the circuit operation. d) Find the circuit (or the logic equation, or the truth table) required to drive the second 7- segment display, to correctly present the tens. Block diagram and pins description of CD4040 are in the drawing. Datasheets of other devices are available from the manufacturers sites. 3

4 2.3 D/A Conversion This part of the exercise brings to the realization of a D/A converter based on a set of weighted resistors (ratio 2), directly driven by the counter outputs. The resistor network brings the output Va to a level related with Q3 Q6 counter outputs. Each output Qi provides (through the weighted resistor) a contribution proportional to the weight (bit position i). Q3 is the LSB, Q6 the MSB. The operation of this D/A converter is described more in detail in lesson F2 of Electronic Systems. Connect the 390K, 180K, 100K, 47K resistors between the counter outputs Q3, Q4, Q5, Q6 and the node A (as shown in the figure). If resistor of the list are not available, build reasonable approximations using series or parallel of available devices. CK CD 4040 Q1 Q2 Q3 Q4 Q5 Q6 Q7. Q12 Nominal actual R1 400 kω 390 kω R2 200 kω 180 kω R3 100 kω 100 kω R4 50 kω 47 kω R1 R2 R3 R4 A Va Apply a 100 KHz square wave to the counter clock input. a) Observe the Va signal on the A node, and the four outputs Q3 Q6; explain the wave shape observed on A node, and the relation with square waves on Q3 6. The following steps are refinement of the experiment, for better understanding of Digital to Analog converters operation and error sources. Should be carried out as far as possible, within the time available. b) Add a 820 kω resistor (R5) between Q2 and node A; verify and explain the effect on Va. c) Remove R5, than add a 27 kω resistor (R7) between Q7 and node A; verify and explain the effect on Va. d) How are the steps on Va modified by a 220 kω resistor (R7') in parallel to R7? Explain the reasons of the changes. e) How are the steps on Va modified by replacing the 47 kω resistor (R4) with two 100 kω resistors in parallel? Explain the reason. 4

5 3 - Common mistakes and possible failures. One of the most frequent reason of failures are false contacts in the breadboard. In case of malfunction, apply the following steps: a) Check wiring. b) Verify the value of passive components (use the DMM as required). c) Verify signals and power supply, directly on the IC circuit, touching the pins with the probe metal tip (to identify false contacts between the breadboard and the IC pins). d) If the D/A converter output characteristic appears non-monotone, verify resistor values and their positions in the counter outputs sequence (on Q6 output should be present a square wave at the lowest frequency). 5

6 1. Report form (draft) Exercise 3: Operational Amplifiers and feedback circuits Date: Team ; composition: role name Student ID signature Measurements Report writing Instruments used Instrument Brand and type characteristics Signal generator: Oscilloscope Digital multimeter Breadboard Brief description of goals 6

7 History of the document DDC last revision (italian) PL translation DDC translation verification DDC small corrections DDC adaptation for Tongij lab DDC adaptation for Tongji Electronic systems 7

PLL frequency synthesizer

ANALOG & TELECOMMUNICATION ELECTRONICS LABORATORY EXERCISE 4 Lab 4: PLL frequency synthesizer 1.1 Goal The goals of this lab exercise are: - Verify the behavior of a and of a complete PLL - Find capture