Figure 1: Structure of N-channel JFET

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1 JUNCTION FIELD EFFECT TRANSISTOR. JFET Principles. Unlike the bipolar transistor in which both types of carriers are involved, the junction field effect transistor (JFET) is an unipolar device for which only one type of carrier is used; electrons in n- channel JFET and holes in p-channel. The simplified structure of a JFET in figure 1 shows ohmic contacts at the ends of a rod of n-type silicon with heavily doped layers of p- type silicon on the sides of the rod. Electrons enter the channel at the source S and are collected at the drain D. The control electrode, the gate G, is normally operated at negative potential with respect to source (V GS <0). As the voltage on the gate is made more negative with respect to source, the depletion layer at the reverse biased p-n junction extends into the channel, reducing its effective width and therefore increasing the channel resistance. Hence the channel current, normally called the drain current I D, is a maximum with no signal applied, i.e. V GS = 0. Figure 1: Structure of N-channel JFET The JFET depends for its action on the control of the depletion region. The input signal is normally applied between the gate and the source, i.e. via the reversed biased junction and the input resistance is therefore very high. The JFET can be considered to be a voltage controlled device because negligible current is demanded from the signal. The drain current characteristics are shown in figure 2. Two distinct regions are apparent: (i) For low values of V DS the FET behaves like a voltage controlled resistor. This region is called the linear region. revnum: 10 1

2 (ii) For higher values of V DS the FET behaves like a constant current source (I D is virtually independent of V DS ). This is the saturation region. The explanation for the drain current departure from the linear characteristic is that the width of the channel tends to decrease with increasing I D even if the gate voltage is kept constant. The narrowing of the channel comes about because of the ohmic resistance of the channel gives rise to a voltage difference between the source and the drain end of the channel. This means that the reverse voltage between the gate and the drain end of the channel increases with the drain current flow, thus reducing the channel width. The saturation is reached when the drain to gate voltage V DG exceeds the, so called, pinch-off voltage V p. The V p and the value of the saturation current I DSS can be most easily determined from the drain characteristic curve for V GS =0 (see figure 2). Both these values are characteristic transistor parameters which are quoted in the transistor data sheets. revnum: 10 2

3 Figure 2: Drain Characteristics of N-channel JFET revnum: 10 3

4 If V GS is non zero, we can still determine the minimum value for which the JFET remains biased for the saturation region. To do so rewrite the condition for JFET saturation V DG > V p expressing the V DG as to give V DG = V DS - V GS V DG > V p + V GS = V p - V GS (1) Analytic Modelling of Drain Characteristics *. It is possible to derive semi-empirical analytical expressions for the drain current. In the linear region I D = 2 I DSS V 1 - V GS p V p. V DS (2) from which the dynamic resistance r ds can be calculated as In the saturated region r DS = V DS I D I D = I DSS. 1 - V GS V 2 p (3) Transconductance g m : The transconductance g m measures the slope of the I D against the V gs and its alue depends on the operating point : g m = di D dv GS = d {I DSS (1 - V gs /V p ) 2 } d V gs = - 2 I DSS V p (1 V gs /V p ) = 2 V p I D.I DSS The square root dependency on the I D indicates that a JFET amplifier will suffer less non-linear distortion than a bipolar one. On the other hand, a typical value of g m for a JFET will be of the order of 5mS which is at least an order of magnitude lower than it is for a bipolar transistor. The JFET is operated in the saturation region when it is used as an amplifier or a switch. When a JFET is used in the first stage of the amplifier, it is in order to obtain a virtual isolation of the signal source whilst keeping the noise contribution low. Bipolar transistors often follow this JFET input stage to boost the signal current available as a JFET has a relatively large output impedance. Some JFETs are specifically designed for use as voltage controlled resistors and operated in the linear region. revnum: 10 4

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6 Biasing of JFET. Figure 3: JFET Constant Current Source Figure 3 shows an arrangement whereby the JFET, biased into saturation, is used as a constant current source. The reverse gate bias V GS is being developed across the R S V GS = - I D.R S (4) Substituting into the condition for saturation (1) we obtain a limiting condition on the value of the load V DG > V p V DD - I D.R L > V p R L < V DD - V p I D Note that there is no restriction on the size of R S. The value of the R S resistor controls the V GS and sets the source current I D. The relationship between I D and R S can be obtained by substituting (4) into (3) and solving for I D. The quadratic equation in I D has only one real positive solution which is given by I D = I DSS. 1 - I D.R S V 2 p (5) and is valid for I D.R S < V p. An alternative view of the DC bias can be obtain from the graphical representation shown in figure 4. Here the operating point Q is determined by the intersection of the drain current characteristic (in saturation) with the load line due to the resistor R S. revnum: 10 6

7 Figure 4: Graphical Analysis of JFET dc Bias. Figure 5 shows a dc bias arrangement for the common source amplifier. The gate potential is kept at the ground level by a large resistance R G. Alternatively, R G can be removed altogether provided that the gate is not left floating but is connected to the output of the previous stage. The source voltage will be above the ground level by the virtue of the potential drop developed across R S. Figure 5: DC Bias of Common Source JFET. When designing a JFET amplifier stage one has to ensure that the transistor is biased in the saturation region. Given a bias current I D the value of R S is determined by solving (5) for R S or from the graphical analysis in figure 4. The maximum size of R D is then given by revnum: 10 7

8 V DG > V p V DD - I D.R D > V p R D < V DD - V p I D Unlike the bipolar transistor, the voltage difference between the gate and the source varies considerably depending on the value of I D in accordance with formula (3). The maximum value for V GS is zero, which corresponds to I D = I DSS, and the minimum value is - V p, which occurs when I D = 0. Consequently, the input signal on the gate has to be kept within the bounds imposed by the saturation requirement (1): V Gmax = V DD - V p - I DSS.R D V Gmin = - V p where V Gmax and V Gmin are the maximum and the minimum gate voltage (with respect to the ground) for which the JFET stage remains in saturation. The problem with these and similar theoretical calculations is that both the I DSS and the V p vary widely between transistors of the same type. For this reason only their range can be given in the data books. If a required dc operating point is to be obtained in spite of the uncertainty in I DSS and V p, more elaborate biasing has to be used. Examples of Practical Biasing. Figure 6: Constant Current Sink JFET Bias. The value of I D may be controlled quite accurately by replacing the resistor R S with a constant current sink. In figure 6 the bipolar transistor Q 2 maintains an approximately constant drain current through the resistor R B. This is because the dc bias condition of this transistor is self-adjusting in keeping the voltage drop across R B constant and equal to V be. The drain current is thus set by the value of R B : revnum: 10 8

9 I D = V be R B = 0.7 R B As mentioned earlier, the gate to source voltage offset varies with the size of I D. It also happens to be fairly unpredictable as it depends on V p (see equation 2). The solution, which minimises the variations in the gate offset, is to use a pair of matched JFETs as shown in figure 7. Figure 7: Dual JFET Bias. The circuit is powered from a symmetrical split power supply. As both transistors are matched (their respective I DSS and V p are the same) and both conduct the same I D, their gate to source voltages have to be the same. This means that the output terminal has to have the same potential as the gate of the transistor Q 1, which, in the absence of a signal, is at the ground level. Thus there is no dc level shift between the input and the output terminal. The zero level shift is particularly desirable in the dc instrumentation amplifiers and the arrangement shown in figure 7 is used as a basis for the input stage of many oscilloscopes. revnum: 10 9

10 MOSFET DC Characteristics. DE MOSFET. With respect to figure 1, explain the operation of the Enhancement Depletion MOSFET. Discuss: - there is always a conducting channel - the gate is insulated from channel by an oxide layer - modulation of channel width is caused by inversion of n material - gate can be positive or negative with respect to channel Inversion : When gate negative with respect to n - channel the layer adjacent to the gate will invert to a p - type material thus reducing the channel width. When gate positive with respect to n - channel the layer the channel will widen. revnum: 10 10

11 Figure 1. revnum: 10 11

12 Gate and Drain Characteristics. Figure 2. The analytical expression for the gate characteristics in the saturation region is: Note: I D = K (V GS - V T ) ² the threshold voltage V T is negative and K = I DSS /V T ² revnum: 10 12

13 Enhancement MOSFET. Figure 3. Discuss: - there is no conducting channel between drain source - the gate is insulated from channel by an oxide layer - the channel becomes conductive because of inversion into n-material - gate should be positive with respect to channel Inversion : When gate is positive with respect to p-channel the layer adjacent to the gate will invert to a n-type material thus forming a conductive channel. When gate is more positive with respect to n-channel the inverted channel widens. revnum: 10 13

14 Gate and Drain Characteristics: jfetdc.doc The analytical expression for the gate characteristics in the saturation region is: Note : I D = K (V GS - V T ) ² the threshold voltage V T is always positive OVERALL : ALL FET characteristics have the same shape revnum: 10 14

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16 DC Bias of Common Source JFET. Two types of problems possible: Problem 1:Given I d, V d find the values of R S and R d (assuming JFET is in saturation). Problem 2:Given R S and R d find the values of I d and V d (assuming JFET is in saturation). Problem 1: Given I d = 1mA, V d = 6V find R S and R D if V dd = 10V, Solution: a) R D = V dd - V d I d = = 4kΩ. I DSS =4mA, V p =3V. b) Check if JFET is in saturation: V DG > V p? V DG = V D = 6V > V p = 3 V yes!!! c) Use graph of JFET I d versus V GS to calculate V GS : from I d = I DSS 1 - V GS V 2 p V GS = V p 1 - I d I = 3 x 0.5 = 1.5V DSS d) R S = V GS I d = = 1.5 k Ω. revnum: 10 16

17 Problem 2: Given R S = 1kΩ, R D = 4kΩ find I D and V d if V dd = 10V. V p = 4V and I DSS = 8mA. Solution : a) Use graph of I d versus V GS to calculate I d (= 2mA) b) Calculate V d : V d = V dd - I d R d = 10-2mA x 4kΩ = 2V c) Check whether JFET is in saturation. V DG = V d = 2V V p = 4V We have: V DG < V p NO SATURATION!!! To correct this : (i) (ii) We may want to make V d > 4, for example by reducing the value of R d to less then 2kΩ or To increase the V dd revnum: 10 17

18 Alternative Solution : Use equation I d = I DSS 1 - V GS V 2 p to calculate I d. Substitute for V GS = R S I d to get I d = I DSS 1 - (R S I d ) V 2 p This gives a quadratic equation: 500 I d 2-5 I d + 8 x 10-3 = 0 I d1 =8mA I d2 = 2mA The solution Id 1 gives V GS = 8mA x 1 kω = 8V This is impossible as V GS cannot be larger than V p = 4V!!! revnum: 10 18

19 AC ANALYSIS of FET AMPLIFIERS. AC Small Signal FET model. Figure 1: Common Source FET Model PARAMETER transconductance gate to channel resistance drain (dynamic) resistance TYPICAL VALUE g m ~ 5 ms r gs ~ 10 MΩ r d ~ 100 kω Common Source Amplifier without Source Resistor: Figure 2: Common Source FET Amplifier revnum: 10 19

20 AC Equivalent Circuit. Figure 3: AC Equivalent circuit of amplifier in figure 2. Voltage Gain A v. A v = v out v in = - i d. (r d R D ) v gs = - g m.v gs. (r d R D ) v gs = - g m. (r d R D ) AC Output Impedance. R out ~ (r d R D ) AC Input Impedance (at low frequencies): R in ~ very large of the order of tens of MΩ revnum: 10 20

21 Analysis of Common Source FET. Voltage Gain A v : Figure 4: Common Source Amplifier. Assume r d >> R D. But v G = v in, so that v out = - R D.i D = - R D.g m.v GS = - R D.g m.(v G - v S ) (1) Substituting for v S to (1) v S = i D.R S =- v out R D R S A v = v out v in = - g m.r D 1 + R S.g m revnum: 10 21

22 Analysis of Source Follower. The source follower stage is shown in figure 5. Figure 5: JFET P-Source Follower The voltage gain can be determined by noting that v in = v G and v out = v S, so that we may express the ac output voltage through v GS v out = R S. i D = R S.(g m.v GS ) = R S. g m. (v G - v S ) = R S. g m.(v in - v out ) Writing v out in terms of v in one obtains v out = R S.g m 1 + R S.g m v in Typically g -1 m is between 200 and 500Ω, so if we choose R S in the same range the voltage gain of the source follower may be significantly smaller than unity. Output Impedance of Source Follower: Figure 6: Output Impedance of Source Follower. In order to calculate the output impedance of the source follower we short its input to the ground and apply an ac voltage v o to its output (figure 2). revnum: 10 22

23 The current resultant i o flowing to the output is the difference between the current i S through R S a the drain current i D. i o = i S - i D (1) But i S = v o R S, so that i D = g m.v GS = g m.(v G - v S ) The input is grounded, so v G = 0, and we obtain i D = -g m.v S = -g m.v o Substituting the above expressions into (1), we obtain i o = V o R S + v o.g m From this, the output impedance r out can be calculated as r out = v o i o = g m -1 RS Now, to keep the voltage gain close to unity, R S has to be larger than g -1 m. In effect, the output impedance is determined by the inverse of the JFET transconductance. It should be noted that r out of the source follower is at least an order of magnitude higher than that of a emitter follower. revnum: 10 23

24 Input Capacitance of FETs. Stray Input Capacitance. Because of the high input impedance of JFET, the effect of the stray inter-electrode capacitances is more pronounced than it is for bipolar transistors. Refer to figure 1 : C in shunting the gate to the ground of a sum of the gate to source stray capacitance C GS and the so called Miller capacitance C Miller. C in = C GS + C Miller Figure1 : Interelectrode Input Capacitance Derivation of Miller Effect : - Miller effect occures where there is inverting voltage gain accross the feedback capacitance C F. - It applies to any amplifier, not only FETs. From the definition of capacitance Figure 2: Miller Effect But C in = i in ω v in revnum: 10 24

25 i in = i f = (v o - v in ) C f ω = v in ( A v + 1) C f ω The Miller capacitance, resulting from the gate to drain parasitic capacitance C GD, is C Miller = (1 + A v ) C GD. where A 1 is the common source voltage inverting gain. Example : The JFET inter-electrode capacitances are quoted in the data sheets. Although they may be small in value, they are not always insignificant even at relatively low frequencies. For example, let us suppose that we have C GD = 3.5pF and C GS = 10pF and the common source amplifier gain is 30 then (i) Calculate input Capacitance : (ii) Calculate the higher critical frequency: C in = 10pF + 31 x 3.5pF = pf Let R G = 1MΩ. f c = 1 2π R G. C in = 1 2π 10 6 x = 14.5 khz When substituted into the above expression: C in = v in ( A v + 1) C f ω = ( A ω v v + 1) C f in If A v is large (i.e. A v >>1) then C in A v C f Stray Input Capacitance. Because of the high input impedance of JFET, the effect of the stray inter-electrode capacitances is more pronounced than it is for bipolar transistors. Figure 4 shows the stray input capacitance C in revnum: 10 25

26 shunting the gate to the ground. This capacitance consists of a sum of the Miller capacitance C m and a capacitance C G. The Miller capacitance, resulting from the gate to drain parasitic capacitance C GD, is C m = C GD. (1 - A v1 ) where A v1 is the common source voltage gain. Similarly, C G, which is due to the gate to source parasitic capacitance C GS, is given by C G = C GS.(1 - A v2 ) where A v2 is the common drain voltage gain (A v2 < 1). Figure 4: Interelectrode Input Capacitance The JFET inter-electrode capacitances are quoted in the data sheets. Although they may be small in value, they are not always insignificant even at relatively low frequencies. For example, let us suppose that we have C GD = 3.5pF and C GS = 10pF and the common source amplifier gain is 5 then with the preceding stage output impedance R G = 1kΩ the 3 db drop frequency f 3 is not very high: f 3 = 1 2π.C in.r G Ω 5MHz The way to increase f 3 is to shunt the gate to ground with a inductance L, so as to make the parasitic input capacitance C in resonate at f 3. The required value of the inductance L is calculated from the parallel resonant circuit formula L = 1 1 (2π.f 3 )² C in The above described method is termed input shunt peaking. An alternative way to extend the f 3 frequency is to reduce the effect of the Miller capacitance, which is the dominant factor in C in. Cascode Circuit. The circuit shown in figure 5, the so called cascode circuit, uses two transistors. The transistor Q 1, in the common source configuration, feeds the signal to the source of the transistor Q 2, the latter being biased in the common gate configuration by shorting its gate to the ground via the C G capacitor. The revnum: 10 26

27 input impedance to the source of a common gate biased JFET equals to the inverse of the transconductance g m2 of the Q 2 transistor. Thus the voltage gain A v1 on the drain of the first transistor, using the formula (3), is A v1 = - g m1 1 g m2 1 + g m1.r S Figure 5: Cascode JFET Stage If the two transistors are similar, given that their drain currents are identical, g m Ω g m2. Thus A v = g m1. R S which has a magnitude smaller than unity. Therefore, the Miller capacitance C m : is also small. C m = C GD. ( 1 - A v1 ) The voltage gain A v of the cascode stage is determined by expressing the output voltage v o v o = - R D. i D = - R D. (g m2. v GS ) = - R D.g m1. (V G2 - V S2 ) But v g2 = 0, as the gate is grounded via C G. Substituting for V S2 = A v1.v in, we can express the gain A v = v o v G1 = - R D.g m1 1 + R S.g m1 The cascode circuit may be also used with bipolar transistors, where similar considerations apply. revnum: 10 27

28 Effect of Output Capacitance*. Figure 6: Drain Peaking of Common Source JFET. The stray output capacitance C S between the drain and the ground can also affect the frequency response. The corresponding 3dB frequency is given by 1 2π.R D.C S Figure 6 shows the output peaking of the drain circuit, which will extend the 3dB drop frequency beyond the above value. The series inductance L is set to resonate out the stray capacitance C S. The required value of L is L = ½ R D ². CS but due to the low Q of the resonant circuit, the value of L is not critical. revnum: 10 28