PROBLEMS. Module 2: Number System DECIMAL NUMBERS. 1. Subtract from 1100 using the 2s complement method show direct subtraction for comparison.

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1 PROBLEMS Module : Number System DECIMAL NUMBERS. Subtract 0 from 00 using the s complement method show direct subtraction for comparison.. Convert the following decimal numbers to binary i 58 0 iv. 8 0 v. 9 0 v Convert each of the following octal numbers to binary i 47 8 iv Represents each of the following binary number by its octal equivalent i 000 iv Add the following hexadecimal numbers A 6 Page of

2 6. Convert each of the following octal numbers to Decimal numbers Convert the given hexadecimal numbers to Decimal numbers AB59C.AC 8. Count from 0 to in radix 5 Module : Number Base Conversions 9. Write the decimal equivalent of (0AB) 6 0. Perform the following : (i) (00000) = (?) 8 = (?) 6 (ii) (40) 0 = (?) (iii) (8) 0 (9) 0 using s and s complement method (iv) (00) + () (v) () 8 + (6) 8. Represents each of the following binary number to hexadecimal numbers Convert each of the following hexadecimal numbers to binary numbers 7A.B DE6.7A. Convert the given octal number to binary number 4. Convert 9 0 to binary 5. Convert.75 0 to binary 6. Convert the given numbers to decimal Page of

3 7. Find the s Complement of Perform the indicated operation A5C4+9A5 A9F9+BCDA 9. Perform the subtract operation on CB966 & 9FC 0. Perform the indicated operation 64 8 X 64 8 FC 6 X DE 6. Perform the following Module 4: Boolean Algebra and Basic Operators. Simplify the given Boolean equation. Reduce the given expressions using Boolean theorems J = F = 4. Using the Boolean algebra postules and theorems simplify the given expressions Z = S = 5. Simplify the following using Boolean postules i 6. Apply DeMorgan s theorem to the following expressions a+b ab+ac i (xy) Page of

4 iv. 7. Simplify using postulates 8. Simplify the using DeMorgan s theorem 9. Prove that 0. Convert the following switching function to a logic diagram use AND, OR & NOT symbols. G = Module 5: Additional Logic Operations. With the help of a logic circuit implement AB + CD = F with three NAND gates. Convert the following equation to a logic diagram use IEEE symbols & realized the equation using AND, OR & NOT gates.. Implement the following using NAND gates and inverters 4. Show how the function can be realized Using AND, OR & INVERTER gates Using NAND gates i Using NOR gates 5. Show how Y = ABC can be implemented with one two input NOR & two input NAND gate. Page 4 of

5 Module 6: Analyses and Synthesis of Combinational Logic Circuits 6. Convert the given equations into SOP form 7. Convert the given equations into POS form 8. Write the given equation in canonical SOP form F(A,B,C) = AC+AB+BC 9. Place the given equation in proper canonical form F(A,B,C)=A+ABC 40. Write the given equation in canonical POS form F(A,B,C)=(A+B)(B+C)(A+C) 4. Place the given equation in proper canonical form Y=A(A+B+C) 4. Express the following SOP equation in a minterm list form 4. Express the following SOP equation in a minterm list form 44. Write the POS equation in a maxterm list form 45. Rewrite the following Boolean expression in M-notation form Page 5 of

6 Module 7: Logic Expression Minimization and Sequential Circuits 46. A part of an excitation table of a SRFF is given in Table. Realize from it: (i) DFF and (ii) TFF. SR Flip Flop Input Present State S R Q n 0 X X For the circuit shown in figure below, investigate the type of flip flop. S Q A B CLK R Q 48. The waveforms given in figure below are applied at the inputs of clocked JKFF. Determine the waveforms at the output Q, if previous state of Q is high. Clearly mark the race around condition on the output waveform, if any. Page 6 of

7 Module 8: Transistor-Transistor Logic (TTL) 49. For the circuit shown in figure find the voltage at the base of transistor Q When The input V IN is at i) logic High ii) Logic low. Vcc 5v R 4k R.6k R 0 Q Q Vin Q Q4 D V0 D R4 k 50. For the TTL NAND gate circuit shown below, both inputs A & B are connected to +5v. Then the state of transistor Q, Q& Q4 is. 5. For the TTL NAND gate circuit shown below, input A is connected to +5v & input B is connected to 0V. Then indicate the state of transistors Q, Q & Q4. Page 7 of

8 5. For the circuit shown below find the condition of base emitter junction & collector base junction of transistor Q, if both inputs A & B are at i) Logic high ii) Logic low. 5. Four open collector AND gates are connected in a wired AND configuration as shown in Fig. 5. Assume that wired AND circuit is driving two standard TTL inputs (-ma each). Determine the minimum value of R if I OL(max) for each gate is 0 ma & V OL(max) = 0.4V. +5V U4A R UA 7408 V UA 7408 UA 7408 Fig. 5. Page 8 of

9 54. A positive going pulse is applied to the input of the circuit shown below. How long will it take for the output pulse to appear? Given t PLH & t PHL = 5ns. Vin HIGH HIGH UA U6A HIGH 55. For a TTL gate V IH(min) =V,V IL(max) =0.8V,V OL(max) =0.4v, V OH(min) =.4v.Determine Low level & High level Noise margin. 56. A certain gate draws µa when its output is high & 5.8µA when its output is low. What is the average power dissipation if V CC is 5v and the gate is operated on a 50% duty cycle? 57. For the circuit shown below what is the logical expression at emitters of transistors Q & Q. VCC=0V Q Q VEE=-5.V A B C 58. For the circuit shown above what is the output at emitters of transistors Q & Q, if all inputs are at i) logic High ii) Logic Low. Page 9 of

10 Answer Keys For Problems i 00 iv v. 00 v i 00 iv i iv FA 7.85 (0) 8.75 (0) ,0,0,0,04,0,,,,4,0, (574) 8 = (ABC) i 9 Page 0 of

11 iv. 0 v. 5. 4FD5 (6). CA.7F (6) () () () 4. 0 () (0) (0) DF69 (6) 66CD 9. C6A (6) 0. 0 DAAC. 0 (5). T=Y AB C. J=PQ 4. Z=ab S= Page of

12 5. A(B C) i Y 6. i iv. (A+B)C 7. Y(X+Z) 8. A B 9. (a+b)(a+c) F(A,B,C) = m (,,7) 44. F(W,X,Y,Z) = m (,6,0,4) 45. F(A,B,C,D) = M (4,5,8,0,,4) Page of

13 T Flip Flop (i). V (ii) Q 0.7 V 50. ON, ON,OFF 5. OFF,OFF, ON 5. i) Base Emitter junction will be Reverse Biased & Collector Base Junction will be Forward Biased. ii) Base Emitter junction will be Forward Biased & Collector Base Junction will be Reverse Biased. 5. R=76.9Ω 54. 5ns 55. V NH =0.4, V NL 56. 7µw 57. Q= A+B+C, Q= 58. i) Q= Logic High,Q= Logic Low. ii) Q= Logic Low, Q= Logic High. Page of