MCM54800A MCM5L4800A MCM5V4800A. 512K x 8 CMOS Dynamic RAM Page Mode SEMICONDUCTOR TECHNICAL DATA

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1 SEMICONDUCTOR TECHNICAL DATA 512K x 8 CMOS Dynamic RAM Page Mode The MCM54800A is a 0.7µ CMOS high speed, dynamic random access memory. It is organized as 524,288 eight bit words and fabricated with CMOS silicon gate process technology. Advanced circuit design and fine line processing provide high performance, improved reliability, and low cost. The MCM54800A requires only 10 address lines; row and column address inputs are multiplexed. The device is packaged in a standard 400 mil J lead small outline package and a 400 mil thin small outline package (TSOP). Three State Data Output Fast Page Mode TTL Compatible Inputs and Outputs Only Refresh Before Refresh Hidden Refresh Self Refresh (MCM54800A only) 1024 Cycle Refresh: MCM54800A = 16 ms MCM5L4800A and MCM54800A = 128 ms Fast Access Time (trac): MCM54800A 70, MCM5L4800A 70, and MCM54800A 70 = 70 ns (Max) MCM54800A 80, MCM5L4800A 80, and MCM54800A 80 = 80 ns (Max) MCM54800A 10, MCM5L4800A 10, and MCM54800A 10 = 100 ns (Max) Low Active Power Dissipation: MCM54800A 70, MCM5L4800A 70, and MCM54800A 70 = 578 m (Max) MCM54800A 80, MCM5L4800A 80, and MCM54800A 80 = 495 m (Max) MCM54800A 10, MCM5L4800A 10, and MCM54800A 10 = 440 m (Max) Low Standby Power Dissipation: MCM54800A, MCM5L4800A, and MCM54800A = 11 m (Max, TTL Levels) MCM54800A = 5.5 m (Max, CMOS Levels) MCM54L800A and MCM54800A = 1.1 m (Max, CMOS Levels) Battery Backup Power Dissipation: MCM5L4800A = 1.7 m (Max, Battery Backup Mode, trc = 125 µs) Self Refresh Power Dissipation: MCM54800A = 1.1 m (Max, Self Refresh Mode) Order this document by MCM54800A/D MCM54800A MCM5L4800A MCM54800A J PACKAE 400 M SOJ E PIN ASSINMENT CC DQ0 DQ1 DQ2 DQ3 NC A0 A1 A2 A3 CC T PACKAE 400 M TSOP E SS DQ7 DQ6 DQ5 DQ4 NC A8 A7 A6 A5 A4 SS PIN NAMES Motorola is announcing the end of life status of the 512Kx8 CMOS (MCM54800A) Dynamic RAM product family. Motorola will accept orders until April 3, 1996, and will support deliveries until October 3, There are no Motorola offerings that will directly replace these devices. A0 A8, Address Input Row Address Strobe Column Address Strobe rite Input Output Enable DQ0 DQ Data Input/Output CC Power Supply (+ 5 ) SS round NC No Connect RE 3 10/95 Motorola, Inc MCM54800A MCM5L4800A MCM54800A 1

2 BLOCK DIARAM DATA IN BUFFER 8 DQ0 DQ8 NO. 2 CLOCK ENERATOR DATA OUT BUFFER A0 A1 A2 BUFFERS (9) DECODER A3 A4 A5 (10) REFRESH CONTROLLER/ COUNTER (10) SENSE AMP I/O ATIN A6 A7 A8 BUFFERS (10) 512 x 8 NO. 1 CLOCK ENERATOR DECODER 1024 MEMORY ARRAY 1024 x 512x 8 SUBSTRATE BIAS ENERATOR CC SS ABSOLUTE MAXIMUM RATINS (See Note) Rating Symbol alue Unit Power Supply oltage CC 1 to + 7 oltage Relative to SS for Any Pin Except CC in, out 1 to + 7 Data Out Current Iout 50 ma Power Dissipation PD 600 m This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Operating Temperature Range TA 0 to 70 C Storage Temperature Range Tstg 55 to C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATIN CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MCM54800A MCM5L4800A MCM54800A 2

3 DC OPERATIN CONDITIONS AND CHARACTERISTICS (CC = 5.0 ± 10%, TA = 0 to + 70 C, Unless Otherwise Noted) RECOMMENDED OPERATIN CONDITIONS (All voltages referenced to SS) Parameter Symbol Min Typ Max Unit Supply oltage (Operating oltage Range) CC SS Logic High oltage, All Inputs Logic Low oltage, All Inputs Except DQ0 DQ7 1.0* 0.8 Logic Low oltage, DQ0 DQ7 0.5** 0.8 * 2.5 at pulse width 20 ns ** 2.0 at pulse width 20 ns DC CHARACTERISTICS Characteristic Symbol Min Max Unit Notes CC Power Supply Current MCM54800A 70, MCM5L4800A 70, and MCM54800A 70, trc = 130 ns MCM54800A 80, MCM5L4800A 80, and MCM54800A 80, trc = 150 ns MCM54800A 10, MCM5L4800A 10, and MCM54800A 10, trc = 180 ns CC Power Supply Current (Standby) ( = = ) ICC2 2 ma CC Power Supply Current During Only Refresh Cycles ( = ) MCM54800A 70, MCM5L4800A 70, and MCM54800A 70, trc = 130 ns MCM54800A 80, MCM5L4800A 80, and MCM54800A 80, trc = 150 ns MCM54800A 10, MCM5L4800A 10, and MCM54800A 10, trc = 180 ns CC Power Supply Current During Fast Page Mode Cycle ( = ) MCM54800A 70, MCM5L4800A 70, and MCM54800A 70, tpc = 45 ns MCM54800A 80, MCM5L4800A 80, and MCM54800A 80, tpc = 50 ns MCM54800A 10, MCM5L4800A 10, and MCM54800A 10, tpc = 60 ns CC Power Supply Current (Standby) ( = = CC 0.2 ) MCM54800A MCM5L4800A and MCM54800A CC Power Supply Current During Before Refresh Cycle MCM54800A 70, MCM5L4800A 70, and MCM54800A 70, trc = 130 ns MCM54800A 80, MCM5L4800A 80, and MCM54800A 80, trc = 150 ns MCM54800A 10, MCM5L4800A 10, and MCM54800A 10, trc = 180 ns CC Power Supply Current, Battery Backup ModeMCM5L4800A Only (trc = 125 µs; t = 1 µs; = Before Cycle or 0.2 ; A0 A8,,, D = CC 0.2 or 0.2 ) CC Power Supply Current, Self Refresh Mode MCM54800A Only ( = = ; A0 A8,,, = CC 0.2 or 0.2 ; DQ0 DQ7 = CC 0.2, 0.2, or Open) ICC1 ICC3 ICC4 ICC5 ICC ma 1, 2 ma 1, 2 ma 1, 2 ma µa ma 1 ICC7 300 µa 1, 3 ICC8 200 µa Input Leakage Current (0 in 7.0 ) Ilkg(I) µa Output Leakage Current (0 out 7.0, Output Disable) Ilkg(O) µa Output High oltage (IOH = 5 ma) OH 2.4 Output Low oltage (IOL = 4.2 ma) OL 0.4 NOTES: 1. Current is a function of cycle rate and output loading. Maximum currents are at the specified cycle time (min) with the output open. 2. Column address can be changed once or less while = and =. 3. t (max) = 1 µs is only applied to refresh of battery back up. t (max) = 10 µs is applied to functional operating. CAPACITANCE (f = 1.0 MHz, TA = 25 C, CC = 5, periodically sampled, not 100% tested) Parameter Symbol Max Unit Input Capacitance A0 A8, Cin 5 pf,,, 7 Input/Output Capacitance ( = to Disable Output) DQ0 DQ7 Cout 7 pf NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I t/. MCM54800A MCM5L4800A MCM54800A 3

4 AC OPERATIN CONDITIONS AND CHARACTERISTICS (CC = 5.0 ± 10%, TA = 0 to + 70 C, Unless Otherwise Noted) READ, RITE, AND READ MODIFY RITE CYCLES (See Notes 1, 2, 3, and 4) Symbol MCM54800A 70 MCM5L4800A 70 MCM54800A 70 MCM54800A 80 MCM5L4800A 80 MCM54800A 80 MCM54800A 10 MCM5L4800A 10 MCM54800A 10 Parameter Std Alt Min Max Min Max Min Max Unit Notes Random Read or rite Cycle Time trelrel trc ns 5 Read Modify rite Cycle Time trelrel trc ns 5 Page Mode Cycle Time tcelcel tpc ns Page Mode Read Modify rite Cycle Time tcelcel tprc ns Access Time from trelq trac ns 6, 8, 9 Access Time from tcelq tcac ns 6, 8 Access Time from Column Address taq taa ns 6, 9 Access Time from Precharge tcehq tcpa ns 6 to Output in Low Z tcelqx tclz ns 6 Output Buffer Turn Off Delay tcehqz toff ns 7 Transition Time (Rise and Fall) tt tt ns Precharge Time trehrel trp ns Pulse idth trelreh t 70 10, , ,000 ns Pulse idth (Page Mode) trelreh tp , , ,000 ns Hold Time tcelreh trsh ns Hold Time trelceh tcsh ns Pulse idth tcelceh t 20 10, , ,000 ns to Delay Time trelcel trcd ns 8 to Column Address Delay Time trela trad ns 9 to Precharge Time tcehrel tcrp ns Precharge Time (Page Mode Only) Hold Time From Precharge (Page Mode Only) tcehcel tcp ns tcehreh trhcp ns Row Address Setup Time tarel tasr ns Row Address Hold Time trelax trah ns Column Address Setup Time tacel tasc ns Column Address Hold Time tcelax tcah ns Column Address Hold Time Referenced to trelax tar ns Column Address to Lead Time tareh tral ns NOTES: (continued) 1. (min) and (max) are reference levels for measuring timing of input signals. Transition times are measured between and. 2. An initial pause of 100 µs is required after power up followed by 8 only refresh cycles or 8 before refresh cycles, before proper device operation is guaranteed. 3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must transition between and (or between and ) in a monotonic manner. 4. AC measurements tt = 5.0 ns. 5. The specifications for trc (min) and trm (min) are used only to indicate cycle time at which proper operation over the full temperature range (0 TA 70 C) is ensured. 6. Measured with a current load equivalent to 2 TTL ( 200 µa, + 4 ma) loads and 100 pf with the data output trip points set at OH = 2.0 and OL = toff (max) and tz (max) define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 8. Operation within the trcd (max) limit ensures that trac (max) can be met. trcd (max) is specified as a reference point only; if trcd is greater than the specified trcd (max) limit, then access time is controlled exclusively by tcac. 9. Operation within the trad (max) limit ensures that trac (max) can be met. trad (max) is specified as a reference point only; if trad is greater than the specified trad (max) limit, then access time is controlled exclusively by taa. MCM54800A MCM5L4800A MCM54800A 4

5 READ, RITE, AND READ MODIFY RITE CYCLES (Continued) Symbol MCM54800A 70 MCM5L4800A 70 MCM54800A 70 MCM54800A 80 MCM5L4800A 80 MCM54800A 80 MCM54800A 10 MCM5L4800A 10 MCM54800A 10 Parameter Std Alt Min Max Min Max Min Max Unit Notes Read Command Setup Time thcel trcs ns Read Command Hold Time tcehx trch ns 10 Read Command Hold Time Referenced to trehx trrh ns 10 rite Command Hold Time tcelh tch ns Read Command Hold Time Referenced to trelh tcr ns rite Command Pulse idth tlh tp ns rite Command to Lead Time tlreh trl ns rite Command to Lead Time tlceh tcl ns Data in Setup Time tdcel tds ns 11 Data in Hold Time tceldx tdh ns 11 Data in Hold Time Referenced to treldx tdhr ns Refresh Period MCM54800A MCM5L4800A and MCM54800A trr trfsh ms rite Command Setup Time tlcel tcs ns 12 to rite Delay tcell tcd ns 12 to rite Delay trell trd ns 12 Column Address to rite Delay tal tad ns 12 Precharge to rite Delay tcehl tcpd ns 12 Setup Time for Before Cycle Hold Time for Before Cycle trelcel tcsr ns trelceh tchr ns Precharge to Active Time trehcel trpc ns Precharge Time ( Before Counter Test) tcehcel tcpt ns Hold Time Referenced to tlreh troh ns Access Time tlq ta ns 6 to Data Delay tlhdx td ns Output Buffer Turn Off Delay Time from thqz tz ns 7 Command Hold Time tll th ns Output Disable Setup Time tlcel tds ns NOTES: 10. Either trrh or trch must be satisfied for a read cycle. 11. These parameters are referenced to leading edge in early write cycles and to leading edge in late write or read write cycles. 12. tcs, trd, tcd, tcpd, and tad are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tcs tcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If tcd tcd (min), tcpd tcpd (min), trd trd (min), and tad tad (min), the cycle is a read modify write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. MCM54800A MCM5L4800A MCM54800A 5

6 SELF REFRESH CYCLE Symbol MCM54800A 70 MCM5L4800A 70 MCM54800A 70 MCM54800A 80 MCM5L4800A 80 MCM54800A 80 MCM54800A 10 MCM5L4800A 10 MCM54800A 10 Parameter Std Alt Min Max Min Max Min Max Unit Notes Pulse idth ( Before Self Refresh, MCM54800A Only) trelrehs ts µs Precharge Time ( Before Self Refresh, MCM54800A Only) Hold Time ( Before Self Refresh, MCM54800A Only) trehrels trps ns trehceh tchs ns READ CYCLE t AR t CSH t t RC t RAD t RCD t RSH t t RAL A0 A8 t RCH t RRH t ROH t AA DQ0 DQ7 OH OL OPEN t A t RAC t CAC t OFF t Z DATA OUT MCM54800A MCM5L4800A MCM54800A 6

7 EARLY RITE CYCLE t RC t t AR t CSH t RCD t RSH t t RAL A0 A8 t RAD t CS t CL t CH t P t CR t DHR t RL t DS t DH DQ0 DQ7 DATA IN MCM54800A MCM5L4800A MCM54800A 7

8 CONTROLLED RITE CYCLE t t RC t AR t RCD t CSH t RSH t RAD t t RAL A0 A8 t CL t P t RL t DS t DH t H t DS DQ0 DQ7 DATA IN MCM54800A MCM5L4800A MCM54800A 8

9 READ MODIFY RITE CYCLE A0 A8 t CSH t RCD t RSH t CRP t t RAD t AR t t RC t AD t CL t RD t CD t P t RL t AA t RAC t CAC t A t D t DS t DH / OH DQ0 DQ7 /OL DATA OUT t DZ DATA IN MCM54800A MCM5L4800A MCM54800A 9

10 FAST PAE MODE READ CYCLE A0 A8 t CRP t RCD t AR t t PC t RAD t CSH t RCH t CP t P t t t CAH ASC t RCH t RSH t RHCP t t RAL t ROH t RCH t A t AA t AA t AA t RRH t CPA t A t CPA t A t CAC t CAC t CACt t RAC t OFF t Z OFF t Z t Z t OFF DQ0 DQ7 OH OL DATA OUT DATA OUT DATA OUT MCM54800A MCM5L4800A MCM54800A 10

11 FAST PAE MODE RITE CYCLE t RCD t AR t PC t CP t P t CP t RSH t CSH t t t t RAL A0 A8 t CL t CL t CL DQ0 DQ7 t CS t CH t t CH CH t RL t CS t CS t P t P t P t CR t DS t DHR t DH t DS t DH t DS t DH DATA IN DATA IN DATA IN MCM54800A MCM5L4800A MCM54800A 11

12 FAST PAE MODE READ MODIFY RITE CYCLE t P t RCD t AR t CSH t PRC t CP t RSH t RAD t t t t RAL A0 A8 COL COL COL t RD t CD t CD t RL t AA t A t CAC t RAC t CD t AD t P t CL t D t Z t CAC t DS t CPA t D t CPD t CL t AD t Z t P t A t AA t DS t CPD t AD t CPA t AA t A t CL t P t D t CAC t Z t DS DQ0 DQ7 /OH / OL t DH t DH t DH DATA OUT DATA IN DATA OUT DATA IN DATA OUT DATA IN MCM54800A MCM5L4800A MCM54800A 12

13 ONLY REFRESH CYCLE t RC t C A0 A8, BEFORE REFRESH CYCLE t RC t C t CSR t CP t CHR DQ0 DQ7 OH OL HIH Z BEFORE SELF REFRESH CYCLE (MCM54800A ONLY) t S S C t CSR C t CP t CHS DQ0 DQ7 OH OL HIH Z MCM54800A MCM5L4800A MCM54800A 13

14 HIDDEN REFRESH CYCLE (READ) t RC t RC t RAD t RCD t t RSH t CHR t A0 A8 t RRH t AA t A t CAC t OFF t Z DQ0 OH DQ7 OL t RAC DATA OUT MCM54800A MCM5L4800A MCM54800A 14

15 HIDDEN REFRESH CYCLE (RITE) t RC t RC t AR t RCD t t CHR t t RAD t RSH A0 A8 t RAH t RAH t CS t CH t P t CR t DHR t DS t DH DQ0 DQ7 DATA IN MCM54800A MCM5L4800A MCM54800A 15

16 BEFORE REFRESH COUNTER TEST CYCLE t CSR t CHR t CPT t t RSH t t RAL A0 A8 READ CYCLE t AA t CAC t RRH t RCH t ROH t A t Z t OFF OH DQ0 DQ8 OL HIH Z DATA OUT RITE CYCLE t CS t RL t CH t CL DQ0 DQ8 t DS t DH DATA IN READ MODIFY RITE CYCLE t AA t AD t CD t CL t RL t P t A t D DQ0 DQ8 / OH /OL HIH Z t CAC DATA OUT t DS t Z DATA IN t DH MCM54800A MCM5L4800A MCM54800A 16

17 DEICE INITIALIZATION On power up, an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight Only refresh cycles or Before refresh cycles to initialize all dynamic nodes within the RAM. During an extended inactive state (greater than 16 milliseconds with the device powered up), a wake up sequence of eight Only refresh cycles or Before refresh cycles is necessary to ensure proper operation. IN THE RAM The ten address pins on the device are time multiplexed at the beginning of a memory cycle by two clocks and will decode one of the 524,288 bit locations in the device. The row address strobe () latches 10 row addresses, and the column access strobe latches nine column addresses. active transition followed by active transition (active =, trcd minimum) follows on all read or write cycles. The delay between and active transitions, referred to as the multiplex window, gives a system designer flexibility in setting up the external addresses into the RAM. There are three other variations in addressing the 512K x 8 RAM: only refresh cycle, before refresh cycle, and page mode. All three are discussed in separate sections that follow. READ CYCLE The DRAM may be read with four different cycles: normal random read cycle, page mode read cycle, read write cycle, and page mode read write cycle. The normal read cycle is outlined here, while the other cycles are discussed in separate sections. The normal read cycle begins as described in - IN THE RAM, with and active transitions latching the desired bit location. The write () input level must be high (), trcs (minimum) before the active transition, to enable read mode. Both the and clocks trigger a sequence of events that are controlled by several delayed internal clocks. The internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex window. Both and output enable () control read access time: must be active before or at trcd maximum, and must be active trac ta (both minimum) to guarantee valid data out (Q) at trac (access time from active transition). If the trcd maximum is exceeded and/ or active transition does not occur in time, read access time is determined by either the or clock active transition (tcac or ta). The and clocks must remain active for a minimum time of t and t, respectively, to complete the read cycle. must remain high throughout the cycle, and for time trrh or trch after or inactive transition, respectively, to maintain the data at that bit location. Once transitions to inactive, it must remain inactive for a minimum time of trp to precharge the internal device circuitry for the next active cycle. Q is valid, but not latched, as long as the and clocks are active. hen either the or clock transitions to inactive, the output will switch to High Z (three state) toff or tz after the inactive transition. RITE CYCLE The user can write to the DRAM with any of four cycles: early write, late write, page mode early write, and page mode read write. Early and late write modes are discussed here, while page mode write operations are covered in a separate section. A write cycle begins as described in IN THE RAM. rite mode is enabled by the transition of to active (). Early and late write modes are distinguished by the active transition of, with respect to. Minimum active time t and t, and precharge time trp apply to write mode, as in the read mode. An early write cycle is characterized by active transition at minimum time tcs before active transition. Data in (D) is referenced to in an early write cycle. and clocks must stay active for trl and tcl, respectively, after the start of the early write operation to complete the cycle. Q remains in three state condition throughout an early write cycle because active transition precedes or coincides with active transition, keeping data out buffers and disabled. A late write cycle (referred to as controlled write) occurs when active transition is made after active transition. active transition could be delayed for almost 10 ms after active transition, (trcd + tcd + trl + 2tT) t, if other timing minimums (trcd, trl, and tt) are maintained. D is referenced to active transition in a late write cycle. Output buffers are enabled by active transition but outputs are switched off by inactive transition, which is required to write to the device. Q may be indeterminate see note 12 of AC Operating Conditions table. and must remain active for trl and tcl, respectively, after active transition to complete the write cycle. must remain inactive for th after active transition to complete the write cycle. READ RITE CYCLE A read write cycle performs a read and then a write at the same address, during the same cycle. This cycle is basically a late write cycle, as discussed in the RITE CYCLE section, except must remain high for tcd minimum after the active transition, to guarantee valid Q before writing the bit. PAE MODE CYCLES Page mode allows fast successive data operations at all 1024 column locations on a selected row of the 512K x 8 dynamic RAM. Read access time in page mode (tcac) is typically half the regular clock access time, trac. Page mode operation consists of keeping active while toggling between and. The row is latched by active transition, while each active transition allows selection of a new column location on the row. A page mode cycle is initiated by a normal read, write, or read write cycle, as described in the prior sections. Once the timing requirements for the first cycle are met, transitions to inactive for minimum tcp, while remains low (). The second active transition while is low initiates the first page mode cycle (tpc or tprc). Either a read, write, or read write operation can be performed in a page mode cycle, subject to the same conditions as in normal operation (previously described). These operations can be intermixed in consecutive page mode cycles and performed in any order. The maximum number of consecutive page mode cycles is limited by MCM54800A MCM5L4800A MCM54800A 17

18 tp. Page mode operation is ended when transitions to inactive, coincident with or following inactive transition. REFRESH CYCLES The dynamic RAM design is based on capacitor charge storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bits in the MCM54800A require refresh every 16 milliseconds, while refresh for the MCM5L4800A and MCM54800A is 128 milliseconds. This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6 microseconds for the MCM54800A, and microseconds for the MCM5L4800A and MCM54800A. Burst refresh, a refresh of all 1024 rows consecutively, must be performed every 16 milliseconds on the MCM54800A, and 128 milliseconds for the MCM5L4800A and MCM54800A. A normal read, write, or read write operation to the RAM will refresh all the bits (4096) associated with the particular row decodes. Three other methods of refresh, only refresh, before refresh, hidden refresh, and self refresh (MCM54800A only) are available on this device for greater system flexibility. Only Refresh only refresh consists of transition to active, latching the row address to be refreshed, while remains high () throughout the cycle. An external counter is employed to ensure that all rows are refreshed within the specified limit. Before Refresh before refresh is enabled by bringing active before. This clock order actives an internal refresh counter that generates the row address to be refreshed. External address lines are ignored during the automatic refresh cycle. The output buffer remains at the same state it was in during the previous cycle (hidden refresh). Hidden Refresh Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding active at the end of a read or write cycle, while cycles inactive for trp and back to active, starts the hidden refresh. This is essentially the execution of a before refresh from a cycle in progress (see Figure 1). Self Refresh (MCM54800A Only) The self refresh is a before refresh where is held low for a period greater than ts (100 microseconds). After this time, an internal timer activates a refresh operation of consecutive row addresses in the dynamic RAM. The self refresh mode is exited when either or transitions to high (). Because of the long periods involved for this method of refresh, it is recommended that the self refresh mode only be used for long periods of standby, such as a battery backup. BEFORE REFRESH COUNTER TEST The internal refresh counter of this device can be tested with a before refresh counter test. This test is performed with a read write operation. During the test, the internal refresh counter generates the row address, while the external address supplies the column address. The entire array is refreshed after 1024 cycles, as indicated by the check data written in each row. See before refresh counter test cycle timing diagram. The test can be performed after a minimum of eight before initialization cycles. Test procedure: 1. rite 0s into all memory cells with normal write mode. 2. Select a column address, read 0 out and write 1 into the cell by performing the before refresh counter test, read write cycle. Repeat this operation 1024 times. 3. Read the 1s which were written in step two in normal read mode. 4. Using the same starting column address as in step two, read one out and write 0 into the cell by performing the before refresh counter test, read write cycle. Repeat this operation 1024 times. 5. Read 0s which were written in step four in normal read mode. 6. Repeat steps one through five using complement data. MEMORY CYCLE BEFORE REFRESH CYCLE BEFORE REFRESH CYCLE DQ0 DQ8 OPEN ALID DATA OUT Figure 1. Hidden Refresh Cycle MCM54800A MCM5L4800A MCM54800A 18

19 ORDERIN INFORMATION (Order by Full Part Number) Motorola Memory Prefix Part Number MCM 54800A XX X XX XX Shipping Method (R2 = Tape and Reel, Blank = Rails) Speed (70 = 70 ns, 80 = 80 ns, 10 = 100 ns) Temperature Range (C = 0 to 70 C) Package (J = 400 mil SOJ, T = 400 mil TSOP) Full Part Numbers MCM54800AJ70 MCM54800AJ70R2 MCM54800AT70 MCM54800AT70R2 MCM54800AJ80 MCM54800AJ80R2 MCM54800AT80 MCM54800AT80R2 MCM54800AJ10 MCM54800AJ10R2 MCM54800AT10 MCM54800AT10R2 MCM5L4800AJ70 MCM5L4800AJ70R2 MCM5L4800AT70 MCM5L4800AT70R2 MCM5L4800AJ80 MCM5L4800AJ80R2 MCM5L4800AT80 MCM5L4800AT80R2 MCM5L4800AJ10 MCM5L4800AJ10R2 MCM5L4800AT10 MCM5L4800AT10R2 MCM54800AJ70 MCM54800AJ70R2 MCM54800AT70 MCM54800AT70R2 MCM54800AJ80 MCM54800AJ80R2 MCM54800AT80 MCM54800AT80R2 MCM54800AJ10 MCM54800AJ10R2 MCM54800AT10 MCM54800AT10R2 PACKAE DIMENSIONS J PACKAE 400 M SOJ E NOTES: 1. DIMENSIONIN AND TOLERANCIN PER ANSI Y14.5M, DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLIN DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. DIM A B C D E F H K L M N P R S MLIMETERS MIN MAX BSC BSC INCHES MIN MAX BSC BSC MCM54800A MCM5L4800A MCM54800A 19

20 T PACKAE 400 M TSOP E L K RAD. RAD. T BASE METAL N F ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ D J DETA A ROTATED 90 C (0.20) M T Z SECTION B-B S DETA A 28 1 R 2 PL B B T- B -Y- A -Z- C (0.010) SEATIN PLANE S 12 PL (0.20) M T Y S NOTES: 1. DIMENSIONIN AND TOLERANCIN PER ANSI Y14.5M, CONTROLLIN DIMENSION: INCH. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION IS.006 (0.15) PER SIDE. 4. DIMENSION D DOES NOT INCLUDE DAM BAR PROTRUSIONS. ALLOABLE PROTRUSION IS.007 (0.18), TOTAL, IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F J K L N R S T MLIMETERS MIN MAX INCHES MIN MAX BASIC BASIC BASIC BASIC BASIC REF 0.10 BASIC REF PL Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi SPD JLDC, Toshikatsu Otsuki, P.O. Box 20912; Phoenix, Arizona F Seibu Butsuryu Center, Tatsumi Koto Ku, Tokyo 135, Japan MFAX: RMFAX0@ .sps.mot.com TOUCHTONE (602) HON KON: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong MCM54800A MCM5L4800A MCM54800A 20 MCM54800A/D