MLR Institute of Technology

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1 MLR Institute of Technology Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad Course Name Course Code Class Branch ELECTRONICS AND COMMUNICATIONS ENGINEERING ASSIGNMENT : DIGITAL DESIGN USING VERILOG HDL : A010 : I I- B. Tech : ECE Year : Course Coordinator : Mr.M.Srikanth Course Faculty OBJECTIVES : Ms.A.Deepthi Designing digital circuits at behavioral and RTL modeling of digital circuits using verilog HDL. verifying these models, and synthesizing RTL models to standard cell libraries and FPGAs. Students gain practical experience by designing, modeling, implementing and verifying several digital circuits. This course aims provide students with the understanding of different technologies related to HDLs, constructs, compile and execute verilog HDL programs using provided software tools. Design digital components and circuits that are testable, reusable and synthesizable. S. No Question 1. Discuss Level of design description. ASSIGNMENT-I UNIT-I INTRODUCTION TO VERILOG HDL Blooms Taxonomy Level Understand Program Out Come A Discuss Level of design description. Understanding B Write short notes on, (a) Concurrency Evaluate N (b) Functional verification Define the following terms relevant to Verilog HDL, Remember I (a). Simulation versus synthesis. (b). PLI (c). System tasks.

2 5 Explain about, (a). Display tasks (b). Strobe tasks Understand K (c). Monitor tasks with examples. N Blooms Taxonomy Program S. No Question Level Outcome Write a syntax functions and tasks with one example. Apply I 8 9 Explain about number system used in Verilog. Understand K Write about $readmemb with example. Apply I Explain the components of a Verilog module with block diagram. Understand K Write about and differences scalars vectors in Verilog module with Apply F 10 examples ASSIGNMENT II UNIT-II GATE LEVEL MODELING AND MODELING AT DATAFLOW LEVEL Explain clocked RS flip-flop Verilog module and test bench. Understand I Design a D-Flip-flop with gate primitives and write its Verilog code. Create M Design a D flip flop using NAND gates. Create M Write a Verilog code for D flip flop using NAND gates. Apply K Classify delays and explain. Creating K Explain inertial and intra-assignment delays in Verilog. Understand I Design a JK flip flop using NAND gates. Create N Write a Verilog code for JK flip flop using NAND gates. Apply K Explain the design approach of a master slave flip-flop with gate Apply K 9 primitives. (OR) Design a master slave JK flip-flop using NAND gates. 10 Write a Verilog code for master slave JK flip flop using NAND gates. Apply K ASSIGNMENT III UNIT-III BEHAVIORAL MODELING Write short notes on the following with examples, Apply H 1 (a). Intra-assignment delays (b). Delay assignments

3 (c). Zero delay. What are the advantages of multiple always blocks? Explain with example. remembering M Write a Verilog module for a rudimentary serial transmitter module. Apply K Explain multiple always blocks. Understand I

4 Blooms Taxonomy Program S. No Question Level Outcome Write a model using the behavioral modeling style to describe the behavior of Apply K 5 a JK flip- flop using an always statement. 8 (a). Design Verilog module to identify the highest priority interrupts. Create M (b). Write test bench simulation results of above questions with explanation (a). Design module to convert angels in radians to one in degrees. Create M (b). Write Verilog code above question with explanation. Explain blocking and non-blocking statement with examples. Understand I Write a Verilog HDL code for n-bit shift register with an enable input using Apply K 9 blocking assignments. Draw the flowchart for the simulation flow. Understand I 10. OR Explain flowchart for the simulation flow. ASSIGNMENT IV UNIT-IV SWITCH LEVEL MODELING, SYSTEM TASKS FUNCTIONS AND COMPILER DIRECTIVES Define and explain the following terms relevant to Verilog HDL, Remember M (a) Module parameters 1 (b) File-based tasks and functions (c) Compiler directives. Explain parameter declaration and assignments. Understand I Explain type declaration for parameters. Understand I Explain automatic(recursive) function. Understand I 5 Explain about module paths. Understand I Define and explain the following terms relevant to Verilog HDL, Remember M (a) Hierarchical access (b) Path delays. Explain $ finish task with example. Understand I 8 Explain $ random function with example. Understand I 9 Explain asymmetric sequence generator with example. Understand I 10 Explain automatic(re-entrant) tasks with example. Understand I ASSIGNMENT V UNIT-V SEQUENTIAL CIRCUIT DESCRIPTION, COMPONENT TEST VERIFICATION 1 Define hold time. Design a Verilog module for D flip-flop with hold time. Remember N Discuss about setuphold, width and period checks used in Verilog. Write a Remember N Verilog module for D flip-flop using setuphold, width and period checks.

5 S. No Question Blooms Taxonomy Program Level Outcome Design a Verilog module for the following, Create M (i) 8-bit transparent D-Latch (ii) 8-bit register with tri-state output. How does the memory initialization is carried out in Verilog? Explain with Create M the help of an example. What are the rules to be followed to declare and to use the bidirectional Evaluate H 5 lines? Write a Verilog module for PLA. Understand I What is functional register? Write and explain the Verilog module for basic Evaluate H shift register? 8 Design and explain the Verilog module for universal shift register. Create M Explain about shift register that uses separates combinational and Understand I 9 sequential blocks. Also write a Verilog code for the same. 10 Write a Verilog code for -binary up-down counter. Understanding H

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