Memory Structures. Ramon Canal NCD - Master MIRI. Slides based on:introduction to CMOS VLSI Design. D. Harris. NCD - Master MIRI 1

Transcription

1 Memory Structures Ramon Canal NCD - Master MIRI Slides based on:introduction to CMOS VLSI Design. D. Harris NCD - Master MIRI 1

2 Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Serial Access Memories NCD - Master MIRI 2

3 Memory Arrays Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Shift Registers Queues Static RAM (SRAM) Dynamic RAM (DRAM) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) First In First Out (FIFO) Last In First Out (LIFO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM NCD - Master MIRI 3

4 Array Architecture 2 n words of 2 m bits each If n >> m, fold by 2 k into fewer rows of more columns bitline conditioning wordlines bitlines row decoder memory cells: 2 n-k rows x 2 m+k columns n-k n k column decoder 2 m bits column circuitry Good regularity easy to design Very high density if good cells are used NCD - Master MIRI 4

5 12T SRAM Cell Basic building block: SRAM Cell Holds one bit of information, like a latch Must be read and written 12-transistor (12T) SRAM cell Use a simple latch connected to bitline 46 x 75 unit cell write bit write_b read read_b NCD - Master MIRI 5

6 6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: Precharge bit, bit_b bit Raise wordline word Write: Drive data onto bit, bit_b Raise wordline bit_b NCD - Master MIRI 6

7 SRAM Read Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip 1.5 A_b bit word P1 P2 N2 A bit_b N1 N3 A_b bit_b N4 1.0 word bit 0.5 A time (ps) NCD - Master MIRI 7

8 SRAM Read Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip N1 >> N A_b word bit word P1 P2 N2 A bit_b N1 N3 bit A_b bit_b N4 0.5 A time (ps) NCD - Master MIRI 8

9 SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value word bit N2 A P1 P2 A_b bit_b N4 Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 N1 N3 Force A_b low, then A rises high Writability 1.5 A_b A Must overpower feedback inverter 1.0 bit_b 0.5 word time (ps) NCD - Master MIRI 9

10 SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 word bit N2 A P1 N1 P2 N3 A_b bit_b N4 Force A_b low, then A rises high Writability Must overpower feedback inverter N2 >> P A_b bit_b A 0.5 word time (ps) NCD - Master MIRI 10

11 SRAM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell bit bit_b word med weak med A strong A_b NCD - Master MIRI 11

12 SRAM Column Example Read Bitline Conditioning Write Bitline Conditioning word_q1 More Cells 2 word_q1 More Cells 2 bit_v1f H SRAM Cell H bit_b_v1f bit_v1f SRAM Cell bit_b_v1f out_b_v1r out_v1r write_q1 1 data_s1 2 word_q1 bit_v1f out_v1r NCD - Master MIRI 12

13 SRAM Layout Cell size is critical: 26 x 45 (even smaller in industry) Tile cells sharing V DD, GND, bitline contacts GND BIT BIT_B GND VDD WORD Cell boundary NCD - Master MIRI 13

14 Periphery Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry NCD - Master MIRI 14

15 Decoders n:2 n decoder consists of 2 n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates Static CMOS Pseudo-nMOS A1 A0 A word A1 A0 1/ word A0 1 A0 A word0 word0 word1 word1 word2 word3 word2 word3 NCD - Master MIRI 15

16 Decoder Layout Decoders must be pitch-matched to SRAM cell Requires very skinny gates A3 A3 A2 A2 A1 A1 A0 A0 VDD word GND NAND gate buffer inverter NCD - Master MIRI 16

17 Large Decoders For n > 4, NAND gates become slow Break large gates into multiple smaller gates A3 A2 A1 A0 word0 word1 word2 word3 word15 NCD - Master MIRI 17

18 Predecoding Many of these gates are redundant Factor out common gates into predecoder Saves area Same path effort A3 A2 A1 A0 predecoders 1 of 4 hot predecoded lines word0 word1 word2 word3 word15 NCD - Master MIRI 18

20 Sense Amplifiers t p = C V I av make V as small as possible large small Idea: Use Sense Amplifer small transition s.a. input output NCD - Master MIRI 20

21 Sense Amplifiers Bitlines have many cells attached Ex: 32-kbit SRAM has 256 rows x 128 cols 128 cells on each bitline t pd (C/I) V Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly through small transistors (small I) Sense amplifiers are triggered on small voltage swing (reduce V) NCD - Master MIRI 21

22 Differential Pair Amp Differential pair requires no clock But always dissipates static power sense_b bit P1 N1 N2 P2 sense bit_b N3 NCD - Master MIRI 22

23 Clocked Sense Amp Clocked sense amp saves power Requires sense_clk after enough bitline swing Isolation transistors cut off large bitline capacitance bit bit_b sense_clk isolation transistors regenerative feedback sense sense_b NCD - Master MIRI 23

25 Column Circuitry Some circuitry is required for each column Bitline conditioning Column multiplexing NCD - Master MIRI 25

26 Bitline Conditioning Precharge bitlines high before reads bit bit_b Equalize bitlines to minimize voltage difference when using sense amplifiers bit bit_b NCD - Master MIRI 26

27 Twisted Bitlines Sense amplifiers also amplify noise Coupling noise is severe in modern processes Try to couple equally onto bit and bit_b Done by twisting bitlines b0 b0_b b1 b1_b b2 b2_b b3 b3_b NCD - Master MIRI 27

28 Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2 kword x 16 folded into 256 rows x 128 columns Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers NCD - Master MIRI 28

29 Tree Decoder Mux Column mux can use pass transistors Use nmos only, precharge outputs One design is to use k series transistors for 2 k :1 mux No external decoder logic needed A0 A0 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 A1 A1 A2 A2 Y to sense amps and write circuits Y NCD - Master MIRI 29

30 Single Pass-Gate Mux Or eliminate series transistors with separate decoder A1 A0 B0 B1 B2 B3 Y NCD - Master MIRI 30

31 Ex: 2-way Muxed SRAM 2 word_q1 More Cells More Cells A0 A0 write0_q1 2 write1_q1 data_v1 NCD - Master MIRI 31

32 Memory configuratons Multiported memories CAM Memories Serial Access, Queues NCD - Master MIRI 32

33 Multiple Ports We have considered single-ported SRAM One read or one write on each cycle Multiported SRAM are needed for register files Examples: Multicycle processor must read two sources or write a result on some cycles Pipelined processor must read two sources and write a third result each cycle Superscalar processor must read and write many sources and results each cycle NCD - Master MIRI 33

34 Dual-Ported SRAM Simple dual-ported SRAM Two independent single-ended reads Or one differential write bit bit_b worda wordb Do two reads and one write by time multiplexing Read during ph1, write during ph2 NCD - Master MIRI 34

35 Multi-Ported SRAM Adding more access transistors hurts read stability Multiported SRAM isolates reads from state node Single-ended design minimizes number of bitlines worda wordb wordc wordd worde wordf wordg ba bb bc bd be bf bg write circuits read circuits NCD - Master MIRI 35

37 Contents-Addressable Memory Data (64 bits) Address Decoder I/O Buffers Comparand Mask 2 9 Validity Bits Priority Encoder Commands Control Logic R/W Address (9 bits) CAM Array 2 9 words 3 64 bits NCD - Master MIRI 37

39 Serial Access Memories Serial access memories do not use an address Shift Registers Tapped Delay Lines Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Queues (FIFO, LIFO) NCD - Master MIRI 39

40 Shift Register Shift registers store and delay data Simple design: cascade of registers Watch your hold times! clk Din 8 Dout NCD - Master MIRI 40

41 Denser Shift Registers Flip-flops aren t very area-efficient For large shift registers, keep data in SRAM instead Move read/write pointers to RAM rather than data Initialize read address to first entry, write to last Increment address on each cycle clk Din counter counter readaddr writeaddr dual-ported SRAM reset Dout NCD - Master MIRI 41

42 Tapped Delay Line A tapped delay line is a shift register with a programmable number of stages Set number of stages with delay controls to mux Ex: 0 63 stages of delay clk Din SR32 SR16 SR8 SR4 SR2 SR1 Dout delay5 delay4 delay3 delay2 delay1 delay0 NCD - Master MIRI 42

43 Serial In Parallel Out 1-bit shift register reads in serial data After N steps, presents N-bit parallel output clk Sin P0 P1 P2 P3 NCD - Master MIRI 43

44 Parallel In Serial Out Load all N bits in parallel when shift = 0 Then shift one bit out per cycle shift/load clk P0 P1 P2 P3 Sout NCD - Master MIRI 44

45 Queues Queues allow data to be read and written at different rates. Read and write each use their own clock, data Queue indicates whether it is full or empty Build with SRAM and read/write counters (pointers) WriteClk WriteData FULL Queue ReadClk ReadData EMPTY NCD - Master MIRI 45

46 FIFO, LIFO Queues First In First Out (FIFO) Initialize read and write pointers to first element Queue is EMPTY On write, increment write pointer If write almost catches read, Queue is FULL On read, increment read pointer Last In First Out (LIFO) Also called a stack Use a single stack pointer for read and write NCD - Master MIRI 46

47 Other considerations Leakage control Redundancy Flash Memories NCD - Master MIRI 47

48 Suppressing Leakage in SRAM sleep V DD low-threshold transistor V DD V DDL V DD,int sleep V DD,int SRAM cell SRAM cell SRAM cell SRAM cell SRAM cell SRAM cell sleep V SS,int Inserting Extra Resistance Reducing the supply voltage NCD - Master MIRI 48

50 Redundancy Redundant columns Redundant rows Memory Array Row Address Fuse : Bank Row Decoder Column Decoder Column Address NCD - Master MIRI 50

51 Error-Correcting Codes Example: Hamming Codes with e.g. B3 Wrong 1 1 = 3 0 NCD - Master MIRI 51

52 Redundancy and Error Correction NCD - Master MIRI 52

54 Flash EEPROM Control gate Floating gate erasure Thin tunneling oxide n 1 source n 1 drain programming p-substrate Many other options NCD - Master MIRI 54

55 Cross-sections of NVM cells Flash NCD - Master MIRI Courtesy Intel EPROM 55

56 Basic Operations in a NOR Flash Memory Erase cell array BL 0 BL 1 12 V G 0 V WL 0 S D 12 V 0 V WL 1 open open NCD - Master MIRI 56

57 Basic Operations in a NOR Flash Memory Write 12 V BL 0 BL 1 G 6 V 12 V WL 0 S D 0 V 0 V WL 1 6 V 0 V NCD - Master MIRI 57

58 Basic Operations in a NOR Flash Memory 5 V G 1 V S D Read 5 V 0 V BL 0 BL 1 WL 0 0 V WL 1 1 V 0 V NCD - Master MIRI 58

59 Memory Structure: Conclusions 2 L 2 K Bit line Storage cell A K A K11 A L 21 Row Decoder Word line Sense amplifiers / Drivers M.2 K Amplify swing to rail-to-rail amplitude A 0 A K21 Column decoder Selects appropriate word Input-Output (M bits) NCD - Master MIRI 59