Tutorial Problems: Bipolar Junction Transistor (DC Biasing)

Transcription

1 Tutorial Problems: Bipolar Junction Transistor (DC Biasing) 1. Consider the circuit shown in Figure 1. Determine I BQ, I CQ and V CEQ for: (a) β = 75, and (b) β = 150. Assume V BE(on) = 0.7 V. Figure 1 Solution: For dc analysis, the capacitor C C is treated as open circuit. (a) β = 75 The Thevenin voltage source V TH and resistance R TH of the base circuit is found by: The base current I BQ : The collector current I CQ : 1

2 The collector-emitter voltage V CEQ : (b) β = 150 Following the same steps as part (a), 2. Design the circuit shown in Figure 2 such that the voltage drop across R C is V CC and the voltage drop across R E is V CC. Assume β = 100 and V BE(on) = 0.7 V. The quiescent collector current is to be I CQ = 0.4 ma, and the current through R 1 and R 2 should be approximately 0.2I CQ. Figure 2 Solution: The design requires that: 2

3 The collector resistor R C : The emitter resistor R E : (Note: Since I CQ I EQ for reasonably large β, it is safe to conclude that R C = R E = 7.5 kω without causing significant error in calculation. In fact, R C and R E are indistinguishable in practical design due to tolerances in the device values.) The base resistors R 1 and R 2 : (Note: The calculation above has assumed that R 1 and R 2 are in series and have the same current flowing through them, i.e. 0.2I CQ. For accuracy, the complete equation should be written as: I(R 1 ) = I(R 2 ) + I BQ, but since I BQ = I CQ / β = ma is very small compared to I(R 1 ) and I(R 2 ) our assumption is considered valid.) 3. For the circuit shown in Figure 3, let β = 100. (a) Find V TH and R TH for the base circuit. (b) Determine I CQ and V CEQ. (c) If the resistors R C and R E vary by ± 5 %, determine the range in I CQ and V CEQ. (d) Draw the load lines corresponding to the maximum and minimum resistor values and mark the Q-points. Assume V BE(on) = 0.7 V. Figure 3 3

4 Solution: For dc analysis, the capacitor C C is treated as open circuit. (a) The Thevenin voltage source V TH and resistance R TH of the base circuit is found by: (b) The collector current I CQ and the collector-emitter voltage V CEQ : (c) If both R C and R E have a tolerance of ± 5 %, their values can vary between 4.75 kω R C 5.25 kω and kω R E kω. The extreme Q-point values are calculated as follows: R E = kω R E = kω R C = 4.75 kω I CQ = ma V CEQ = 2.33 V I CQ = ma V CEQ = 2.97 V R C = 5.25 kω I CQ = ma V CEQ = 1.60 V I CQ = ma V CEQ = 2.30 V 4

5 (d) The load line of the transistor circuit is given by: With ± 5 % tolerance of the resistance values of R C and R E, the resulting Q-point value (V CEQ, I CQ ) will lie within the shaded region. 4. In the circuit shown in Figure 4, find I CQ such that the Q-point is in the center of the load line. Let β = 75 and V EB(on) = 0.7 V. What are the values of I CQ and V ECQ? Why is it desirable to design the Q- point to be in the center of the load line? Figure 4 5

6 Solution: For the pnp transistor circuit shown, designing the Q-point to be in the center of the load line requires: The Thevenin voltage source V TH and resistance R TH of the base circuit is found by: The base current I BQ is found by writing KVL equation around the base circuit with the emitter current I EQ flowing into the emitter and the base current I EQ flowing out of the base: Since V ECQ = 6 V, A maximum swing of input and output voltage is achieved when the Q-point is in the center of the load line. 6

7 5. (a) For the circuit shown in Figure 5, design a bias-stable circuit such that I CQ = 0.8 ma and V CEQ = 5 V. Let β = 100 and V BE(on) = 0.7 V. (b) Using the results of part (a), determine the percentage change in I CQ if β is in the range 75 β 150. (c) Repeat part (a) and (b) with R E = 1 kω. What can you conclude from these results? Hint: As a general rule, a bias-stable circuit requires R TH 0.1(1 + β)r E. Figure 5 Solution: For dc analysis, the capacitors C C1, C C2 and C E are treated as open circuit. The required Q-point has I CQ = 0.8 ma and V CEQ = 5 V when β = 100. (a) The Thevenin voltage source V TH and resistance R TH of the base circuit is expressed by: To design a bias-stable circuit, the following condition must be satisfied: Writing the KVL equation around the base circuit gives: 7

8 Hence Since I CQ = 0.8 ma and V CEQ = 5 V, (b) If β changes over the range 75 β 150, the quiescent collector current I CQ changes according to the equation below. When β = 75, When β = 150, The percentage change in I CQ is: 8

9 (d) If the emitter resistor R E is changed to R E = 1 kω, the calculation is repeated as follows: When β = 75, When β = 150, The percentage change in I CQ is: 6. Design a bias-stable pnp transistor circuit to meet a set of specifications. The transistor Q-point values are to be: V ECQ = 7 V, I CQ 0.5 ma, and V RE 1 V. Assume transistor parameters β = 80 and V EB(on) = 0.7 V. 9

10 Figure 6 Solution: For dc analysis, the capacitor C C is treated as open circuit. The required Q-point has I CQ = 0.5 ma, V ECQ = 7 V when β = 80 and V RE = 1 V. From these data, the collector resistance R C and emitter resistance R E can be found as: The Thevenin voltage source V TH and resistance R TH of the base circuit is expressed by: Writing the KVL equation around the base circuit gives: Hence 10

11 7. The range of β for the transistor in the circuit in Figure 7 is 50 β 90. Design a bias-stable circuit such that the nominal Q-point is I CQ = 2 ma and V CEQ = 10 V. The value of I C must fall in the range 1.75 I C 2.25 ma. Figure 7 Solution: Assume the nominal value of β is given by the mid-range value, i.e. β = ( ) / 2 = 70. From the data given, the emitter resistance R E is found by: For bias-stable circuit, the Thevenin resistance R TH of the base circuit is: Writing the KVL equation around the base circuit gives: 11

12 When β = 50, When β = 90, Hence when the value of β changes between 50 β 90, the value of I CQ falls within the range 1.75 I C 2.25 ma and therefore the design specification is met. 8. The nominal Q-point of the circuit in Figure 8 is I CQ = 1 ma and V CEQ = 5 V, for β = 60. The current gain of the transistor is in the range 45 β 75. Design a bias-stable circuit such that I CQ does not vary by more than 5 % from its nominal value. Figure 8 Solution: Given the nominal value of β is 60. From the data given, the emitter resistance R E is found by: 12

13 For bias-stable circuit, the Thevenin resistance R TH of the base circuit is: Writing the KVL equation around the base circuit gives: When β = 45, When β = 75, Hence when the value of β changes between 45 β 75, the value of I CQ does not vary by more than 5 % from its nominal value and therefore the design specification is met. 13

14 9. In the circuit shown in Figure 9, the transistor Q 0 is biased with a constant current source instead of resistor network. Design the circuit such that V CE0 = 5 V and V CE2 = 3 V, where the subscript 0 and 2 denotes Q 0 and Q 2 respectively. Assume β = 50 and V BE(on) = 0.7 V for all transistors. Figure 9 Solution: The constant current source formed by Q 1 and Q 2 is called the current mirror. Summing all currents at the collector of Q 1 by assuming that Q 1 and Q 2 are identical, we have: 14

15 For the circuit shown in Figure 9, It is required that V CE0 = 5 V and V CE2 = 3 V, hence: 10. For each transistor in the circuit in Figure 10, β = 120 and V BE(on) = 0.7 V. Determine the quiescent base, collector, and emitter currents in Q 1 and Q 2. Also determine V CEQ1 and V CEQ2. Figure 10 15

16 Solution: The base circuit of Q 1 is replaced with the equivalent Thevenin voltage source V TH and resistance R TH with the following values: The base current I BQ1 : The collector current I CQ1 and emitter current I EQ1 : At the collector of Q 1, the following equation can be written: Therefore, 16

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