A Little Perspective Combinational Logic Circuits


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1 A Little Perspective Combinational Logic Circuits COMP 251 Computer Organization and Architecture Fall 2009 Motivating Example Recall our machine s architecture: A Simple ALU Consider an ALU that can perform the following operations: ADD, SUB, AND, OR, NOT C3 C2 C1 C0 Operation B A B A & B A + B ~B A  B All of the computations that can be performed in our assembly/machine languages have to be able to be carried out by the hardware. ADD, SUB, AND, OR, SHL, SHR etc A, B, R 32 bit binary C3C0 1 bit control lines N, Z, O 1 bit status flags Result is Negative, Zero, Odd Binary Addition Consider the process of adding two, 2 s complement binary numbers: or With the second approach we can see that the bit in every column is generated as the addition of 3 bits. Thus, to build a machine that can add n bit binary numbers we need only build n copies of a machine that can add three 1 bit binary numbers. Binary Addition Adding three, 1 bit binary numbers: 1 x 1 or more generally y z 10 c s s sum of three bits c carry out to next bit. Adding multibit numbers: 1
2 Building Blocks Logic Gates: Electronic components that compute a Boolean function of their inputs. Logic Circuits Logic Circuit: A combination of logic gates that computes some Boolean function. Every circuit can be expressed in three ways: Logic Expression Truth Table Logic Expression z = AB + C Truth Table A B C Z More Building Blocks Some additional logic gates that we ll use: Schematic Expression Converting a Schematic to an Expression: Write expressions for intermediate results. Write expression for output in terms of intermediate results. Substitute intermediate results into output expression. Logic Expression Z = AB + (A + B) Schematic Truth Table Converting a Schematic to a truth table: Write out all possible inputs. Generate truth values for intermediate results. Generate the truth vales for the output. Truth Table A B C D Y Z Truth Table Expression Converting a Truth Table to an Expression: Generate an AND term for each row of the truth table with output 1. OR together all of the AND terms. This gives an expression in SumOfProducts (SOP) form. Truth Table A B C Z Expression Z = ABC + ABC + ABC + ABC Note: AB AB 2
3 SOP Expression Schematic Converting SOP Expressions to Schematics: Expression Z = ABC + ABC + ABC + ABC Typical Problem Construct a circuit that detects prime numbers in 3 bit unsigned representation. Primes: 2, 3, 5, 7 Approach? Probe Applet Probe: Circuit simulation program. Available online: See Link on web page. Quick Demo: Click on Start Probe button on web page Select component type Use add new component tool Input Probes Logic Gates Output Probes Truth Table Window Copy: Command+Shift+4 then Space bar Circuit Design Motivating Example: Create a circuit that detects even 3 bit unsigned binary numbers. The input is a 3 bit unsigned binary number (ABC). The output is a single bit (E): 1 if the input is even. 0 if the input is odd. A B C E (0) (1) (2) (3) (4) (5) (6) (7) 0 E = ABC + ABC + ABC + ABC Evaluating Circuit Quality Cost: The total number of inputs on the logic gates gives an estimate of the cost of the circuit. Speed: The maximum number of gates through which an input must pass before reaching the output gives an estimate of the speed of the circuit. Propagation Delay Example 1: Cost = Delay = Example 2: Cost = Delay = Examples 3
4 Logic Simplification Boolean Algebra: The Boolean Algebra consists of a collection of identities that can be used to transform Boolean expressions into other equivalent Boolean expressions that may yield better circuits: Fewer gates or inputs (cheaper) Smaller propagation delays (faster) NOTE: Two Boolean expressions, A and B, are equivalent if and only if all possible inputs that make A true also make B true and vice versa. Boolean Identities Name And Form Or Form Identity 1 A = A 0 + A = A Null 0 A = 0 1+ A =1 Idempotent A A = A A + A = A Inverse A A = 0 A + A =1 Commutative A B = B A A + B = B + A Associative (A B) C = A (B C) (A + B) + C = A + (B + C) Distributive A + (B C) = (A + B) (A + C) A (B + C) = A B + A C Absorption A (A + B) = A A + A B = A DeMorgan's A B = A + B A + B = AB Double Negation A= A Exercises Simplify the following circuits to minimize the propagation delay: Circuit 1: Exercises Simplify the following circuits to minimize propagation delay: Circuit 3: Circuit 2: Circuit 4: Exercises Simplify the following circuit to minimize propagation delay: Circuit 5: Recall Our ALU Our ALU that can perform the following basic operations: ADD, SUB, AND, OR, NOT C3 C2 C1 C0 Operation B A B A & B A + B ~B A  B A, B, R 32 bit binary C3C0 1 bit control lines N, Z, O 1 bit status flags Result is Negative, Zero, Odd 4
5 Our ALU In reality the basic operations of our ALU will be controlled by C1 and C2 and will consist of only: Inside Our ALU Recall the carryripple approach to addition: C1 C0 Operation 0 0 B 0 1 A B 1 0 A & B 1 1 A + B Additional operations will be enabled by control lines C2 and C3 as follows: C2 If 1, Flip the bits of B before performing operation. C3 Set the carry in to the LSb A similar approach for an n bit ALU: Inside a 1Bit ALU Computing each of the basic operations of the ALU is not difficult: Inside a 1Bit ALU Picking the correct output: Multiplexers Multiplexer (mux): A circuit that uses n control lines (C) to select one of 2 n inputs (D) as the output (Z). Inside a Multiplexer Like all of our other circuits, a multiplexer can be constructed using the basic logic gates. C1 C0 Z 0 0 D D D D 3 Multiplexers come in 2, 4, 8, 16 etc input varieties. 5
6 Inside a 1Bit ALU A full working 1bit ALU: Propagation Delays What is the propagation delay of the result (r i ) and carryout (c) for our 1bit ALU? Propagation Delays What is the propagation delay for an n bit carryripple ALU? Propagation Delays Why are propagation delays important? Recall that generally one machine language instruction will execute during each machine cycle. If that instruction uses the ALU, the length of the cycle must be long enough to allow the ALU to perform its computation. 6
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