CHAPTER 4 ELECTRO-OPTICAL HYBRID LOGIC GATES

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1 54 CHAPTER 4 ELECTRO-OPTICAL HYBRID LOGIC GATES

2 55 CHAPTER 4 ELECTRO-OPTICAL HYBRID LOGIC GATES 4.0 INTRODUCTION This chapter is devoted to describe the circuit structures of electrooptical hybrid logic gates like, hybrid inverter, hybrid NOR, hybrid NAND, hybrid OR, hybrid AND and hybrid EX-OR. To conceive and realize these hybrid logic circuits, optoelectronic devices like Light Emitting Diodes (LED s), and laser diodes which can give optical outputs and three terminal photo detectors like phototransistors, which can respond to optical signals are needed. Since alignment of light source and detectors are involved in realizing hybrid logic circuits, it is proposed to use optocouplers as they are available with perfectly aligned Light Emitting Diode (LED) and the phototransistor in a single IC package. Hence, optocouplers have been used for implementing and verifying the functionality of different hybrid logic circuits. Computer aided circuit analysis provides additional information about the circuit performance that is some times difficult to obtain with laboratory prototype measurements. Hence, to evaluate the hybrid circuit performance under varied conditions (the variations in circuit elements), these circuits have been simulated using OrCAD CAPTURE 10.3 circuit simulation tool which is explained in APPENDIX-A. In order to arrive at circuits for different hybrid logic functions, the characteristics of LED and phototransistor are required. Hence, the characteristics of these optoelectronic devices have been described and simulated using OrCAD CAPTURE circuit simulation tool [ ]. From the device characteristics, electrical and optical logic levels are defined and are used to test the functionality of various hybrid logic gates. 4.1 CHARACTERISTICS OF LED By varying the current through the LED, the intensity of light output is changed. There is no access to measure the light intensity of LED in the optocoupler. An LED model available in the library of OrCAD

3 56 CAPTURE circuit simulation tool has been used to calculate the light output power based on the current flowing through the LED. The Light-Emitting Diode model represents a light-emitting diode as an exponential diode in series with a current sensor. The LED model has three ports: W-port is optical output power, p-port is electrical conserving port associated with the diode positive terminal and n-port is electrical conserving port associated with the diode negative terminal. The optical power presented at the signal port w is equal to the product of the current flowing through the diode and the optical power per unit current parameter value. The LED parameters of 4N32 optocoupler which are used in the simulation are given in Table.4.1. The Circuit diagram for simulation of LED characteristics is shown in Fig.4.1. The output power versus forward current (the forward current is varied by varying the input voltage Vi) characteristics of LED in 4N32 optocoupler is shown in Fig.4.2. A measure of light intensity is obtained by noting the current through the LED from the characteristics given in Fig.4.2. The V-I characteristics of LED present in the optocoupler have also been simulated and is given in Fig.4.3. Table4.1. Simulation parameters of LED LED property Description Value IS LED saturation current 77fA N LED emission coefficient 1.76 RS LED series resistance 2 Ω CJO LED zero bias junction capacitance 18pF M LED CJ exponent 0.5 VJ LED contact potential 1V ISR LED reverse current 0.05µA BV LED breakdown voltage 3V IBV Reverse breakdown knee current 10µA TT Transit time 5ns

4 57 LED R 1 386Ω V 1 0-5V W-PORT Fig.4.1 Circuit diagram for obtaining LED characteristics. 12mA 1 12mW 2 10mW 1 8mA 8mW 2 Forward current IF 6mA Output power Po 6mW 4mA 4mW 2mA 2mW 1 2 0W 0.5V V V V 5. Input voltage V 1 Fig.4.2 Forward current and output power of LED as a function of input voltage V1.

5 58 12mA 8mA Forward current IF 6mA 4mA 2mA 0.1V 0.2V 0.3V 0.4V 0.5V 0.6V 0.7V 0.8V 0.9V V 1.2V Forward voltage Fig.4.3 V-I characteristics of LED. From the above characteristics, it may be noted that LED output power is 0mW for IF=0mA and 10mW for IF =. The forward voltage VF across the LED is 1.15V for IF =. 4.2 CHARACTERISTICS OF PHOTOTRANSISTOR The response of phototransistor for input light can t be measured in the optocoupler IC and therefore has been simulated using OrCAD CAPTURE simulation tool. Instead of using the light intensity as the input parameter, the equivalent LED current (IF) has been used. The circuit diagram for obtaining the characteristics of phototransistor in 4N32 optocoupler is shown in Fig.4.4. In this circuit, V1 is the input supply voltage used to changed the forward current (IF) through LED, Vi is the electrical input voltage to change the base current (IB) of phototransistor (PT), VCE is the collector to emitter voltage of PT, IC is the collector current of PT, or R1 is the current limiting resistor flowing through LED, RB is the base current limiting resistor of PT. The characteristics obtained includes, IF versus IC for constant VCE (transfer characteristics), V1 versus IC and output characteristics of phototransistor (IC versus VCE for different base

6 59 currents) respectively. The forward current (IF) through LED is varied by changing the input voltage (V1) in steps. These characteristics are obtained using OrCAD CAPTURE tool and the simulated characteristics are given in Fig.4.5, Fig.4.6 and Fig.4.7. R B I B V i R 1 386Ω IF IC V 1 4N32 6V V CE Fig.4.4 Circuit diagram for obtaining the characteristics of 4N32 optocoupler. 240mA 200mA I B = 10 µa 160mA I B = 8 µa 120mA I B = 6 µa IC (ma) 80mA I B = 4 µa 40mA I B = 2 µa 0.5V V V V 5. V CE (V) Fig.4.5 Output characteristics of phototransistor (VCE Vs IC).

7 60 Fig.4.6 Transfer characteristics of 4N32 optocoupler (IF versus IC). 8mA 6mA Collector voltage IC 4mA 2mA 0.5V V V V 5. Input voltage V 1 Fig.4.7 Transfer characteristics of 4N32 optocoupler (V1 versus IC).

8 61 From the above transfer characteristics, it may be noted that the phototransistor collector current IC=9.6mA for V1=5V. The optoelectronic device characteristics obtained above will enable the implementation of hybrid circuits in terms of voltages and currents. To realize the hybrid inverter function, the hybrid inverter circuit is required to complement or invert the input signal i.e., the output must be LOW if the input is HIGH and vice versa. This is accomplished by diverting the current from the current source into the hybrid inverter circuit. Hence, a current source is needed to implement the hybrid inverter function which is discussed in the following section. 4.3 CURRENT SOURCE A current source is used in the hybrid circuit as a power source. An ideal current source is a circuit element where the current through it is independent of the voltage across it. A current source provides a constant current, as long as the load is connected to the source terminals has sufficiently low impedance. An ideal current source has an infinite output impedance. The collector of a bipolar transistor behaves as current source when properly connected to an external power supply, because the output impedance of this device is high. The circuit diagram of the current source with load resistor RL is shown in Fig.4.8. The current that the current source supplies depends on base resistance (RB) and current gain hfe of the transistor used. This current source configuration is used as a power source for the hybrid logic circuits reported in the thesis. The proposed hybrid inverter has been discussed in the following section. VEE Q R B R L Fig.4.8 Circuit diagram of current source.

9 HYBRID INVERTER Circuit diagram of proposed hybrid inverter, its principle of operation, experimental results and the transient response have been discussed in the following section Circuit diagram of proposed hybrid inverter The circuit diagram of proposed hybrid inverter or hybrid NOT gate is shown in Fig.4.9. It consists of a current source in series with a phototransistor and a load consisting of an LED to provide optical output and a series resistor RL across which electrical output is taken. The phototransistor is used as a switch which can be operated with either electrical or optical input signals. The input to the phototransistor is either current through the base of the phototransistor or the light generated and coupled to the phototransistor due to the current flowing through the source LED. The source LED and the darlington phototransistor are obtained using 4N32 optocoupler. For the sake of simplicity in drawing the circuit diagrams, the darlington phototransistor is shown as simple phototransistor in all circuit diagrams. The Load LED is also obtained from the same 4N32 optocoupler, making sure that source LED and Load LED are identical. The current source is implemented using BC558A transistor. In this circuit, Vi indicates the electrical input and Ii (current through source LED) is the optical input. Vo is the electrical output and Io (current through Load LED) is the optical output of the gate. V1 is power supply voltage used to vary the input current Ii through source LED, VEE is the power supply to the current source, RB1 is the base current limiting resistor of phototransistor, R1 is the current limiting resistor of source LED current, RB is the base resistance of current source and RL is the load resistor.

10 63 R B1 V i VEE V 1 R1 I i source LED 4N32 BC558A Load LED R B Light Output I o V o RL Fig.4.9 Circuit diagram of proposed hybrid inverter Definition of electrical and optical logic level values When the optical input Ii (current through source LED) corresponding to logic HIGH is applied to the phototransistor, the phototransistor is ON and most of the current from the current source flows through it and very small negligible current flows through the Load LED. This small current flowing through Load LED does not produce any light. The output voltage Vo across the load resistor RL is also very small. Thus, a sufficiently large current flowing through source LED produces no light output through the load LED (optical logic LOW) and the output voltage (Vo) across the resistor RL is also small (electrical logic LOW). From the LED characteristics shown in Fig.4.2, it may be seen that a forward current of flowing through the LED produces acceptable light output (10mW). Hence, a forward current (IF) of has been taken as optical logic HIGH. Further, when a forward current (IF) through source LED is 0mA, there is no light from the source LED and the phototransistor is cutoff. In this case, the entire current from the current source flows through the Load LED producing acceptable light intensity corresponding to optical logic HIGH. For the optical logic to be correct, it is required that the output optical logic HIGH and the input optical logic

11 64 HIGH should be almost the same. This condition also decides the value of current supplied by the current source and hence it is fixed at. The application of an electrical voltage (Vi) of value 5V through a series base resistor (RB1) of value 200kΩ is found to keep the phototransistor in saturation, diverting almost the entire source current of flowing through it. This ensures that, almost negligible amount of current flows through the Load LED, giving rise to no light output thus no output voltage. Hence, an electrical logic HIGH corresponding to 5V, produces optical logic LOW (no light) and electrical logic LOW (no output voltage). When there is no input voltage applied i.e., Vi=, the phototransistor is in the cutoff region, the entire current of the current source flows through Load LED, giving rise to light output corresponding to Io of (optical logic HIGH) and an output voltage Vo corresponding to about 5V (electrical logic HIGH). Thus, an input electrical logic LOW produces an optical logic HIGH and an electrical logic HIGH. Table4.2 summarizes the electrical and optical logic levels. Table4.2 Definition of Electrical and Optical Input-Output logic levels LOGIC LEVELS INPUT OUTPUT Electrical logic LOW Electrical logic HIGH 5V 5V Optical logic LOW (current through LED/LED output power) Optical logic HIGH (current through LED/LED output power) 0mA/0mW /10mW 0mA/0mW /10mW To find suitable value of supply voltage (VEE) and other components for the current source, the hybrid inverter circuit has been constructed and its performance has been measured as described below.

12 Experimental results In order to verify the functionality, the proposed hybrid inverter circuit of Fig.4.9 is implemented with a current source of. The collector of BC558A transistor behaves as current source, when connected to a power supply. To generate of current through the current source, a supply voltage of 6.2V with a base resistance (RB) of 87KΩ is used. The voltage drop across the source LED/Load LED is around 1.15V for producing a current of. The value of resistor R1 is selected as 386Ω to provide an input current Ii of through source LED. To produce electrical logic HIGH corresponding to a voltage of 5V, a series load resistor RL of value 500Ω is added to the Load LED. This circuit thus satisfies the conditions that input logic levels and output logic levels are almost the same and is shown in Fig The performance of this circuit for different electrical/optical input logic conditions is shown in Table4.3. R B1 V EE V i V 1 R 1 386Ω I i source LED 4N32 Current Source Load LED I o R B 87KΩ Light Output V o R L 500Ω Fig.4.10 Circuit diagram of hybrid inverter with component values. Table4.3 Input-Output response of a hybrid inverter Electrical input Vi (V) Electrical output Vo (V) Optical output Io (ma) Optical input Ii (ma) Electrical output Vo (V) Optical output Io (ma)

13 Definition of tolerable electrical and optical input-output logic levels and noise margins In order to obtain the variations in the logic levels that can be tolerated by the inverter circuit, electrical input voltage Vi and optical input Ii (source LED current) are varied from to 5V and 0mA to respectively and the corresponding electrical and optical output values are measured and transfer characteristics are plotted. These electrical and optical transfer characteristics are shown in Fig.4.11 and Fig Fig.4.11 Voltage Transfer Characteristics (VTC) of a hybrid inverter. From the Fig.4.11, it may be seen that when the electrical input voltage Vi is, the electrical output voltage is 4.8V and optical output Io (current through Load LED) is 9.6mA. When the electrical input voltage Vi is varied from to 0.65V, the corresponding electrical output voltage Vo varies from 4.8V to 4.4V and optical output Io varies from 9.6mA to 9.2mA. These output variations are relatively small and perhaps tolerable in cascadable logic circuits. Hence, the maximum logic LOW level input voltage is fixed at 0.65V, as the phototransistor starts conducting if the input voltage is greater than or equal to 0.7V. Consider the other extreme case of input i.e., electrical logic HIGH input. When Vi is 5V, electrical

14 67 output voltage is and optical output Io (current through Load LED) is 0mA. From the experimental results obtained, it is found that when the input voltage is varied between 0.7V and 5V, the electrical and optical output variations are relatively small (electrical output is 0.1V and optical output is 0.7mA). From the above discussion and experimental results obtained, the tolerable electrical input-output logic levels and noise margins are defined and are given in Table 4.4, where, VIL is the maximum input voltage that will be recognized as tolerable LOW input logic level, VOH is the minimum output voltage that will be recognized as tolerable HIGH output logic level and VIH is the minimum input voltage that will be recognized as tolerable HIGH input logic level, VOL is the maximum output voltage that will be recognized as tolerable LOW output logic level, NML is the is the electrical low noise margin and NMH is the is the electrical high noise margin. Fig.4.12 Current Transfer Characteristics (CTC) of a hybrid inverter. From the Fig.4.12, it may be noted that that when optical input Ii (current through source LED) is 0mA (no light input), the optical output Io (current through Load LED) is 9.6mA and the electrical output voltage is 4.8V. When the optical input Ii is varied from 0mA to 4.5mA, it is found

15 68 that the electrical output voltage Vo varies from 4.8V to 4.4V and optical output Io varies from 9.6mA to 9.2mA. Consider the other extreme case of input i.e., optical logic HIGH input. When Ii is, the output of the inverter is LOW i.e., Io is 0mA and Vo is. From the experimental results obtained, it is found that when Ii is varied from 6mA to, the electrical and optical output variations are relatively small (electrical output is 0.1V and optical output is 0.7mA). From the above discussion and experimental results obtained, the tolerable optical input-output logic levels and noise margins are defined and are given in Table 4.4, where, IIL is the maximum input current flowing through source LED that will be recognized as tolerable LOW input logic level, IOH is the minimum output current flowing through Load LED that will be recognized as tolerable HIGH output logic level and IIH is the minimum input current flowing through source LED that will be recognized as tolerable HIGH input logic level, IOL is the maximum output current flowing through Load LED that will be recognized as tolerable LOW output logic level, ONML is the is the optical low noise margin and ONMH is the is the optical high noise margin. Table4.4 Tolerable Electrical and Optical Input-Output logic levels and noise margins hybrid inverter. Tolerable electrical logic levels Electrical low noise margin (V) Electrical high noise margin (V) VIL (V) VIH (V) VOL (V) VOH (V) NML = VIL - VOL NMH = VOH - VIH 0.65V 0.7V 0.1V 4.4V Tolerable optical logic levels Optical low noise margin (ma) Optical high noise margin (ma) IIL (ma) IIH (ma) IOL (ma) IOH (ma) ONML = IIL - IOL ONMH = IOH - IIH 4.5mA 6mA 0.7mA 9.2mA Computer aided circuit analysis provides additional information about the circuit performance that is some times difficult to obtain with laboratory prototype measurements. Hence, to evaluate the hybrid inverter circuit performance under varied conditions (the variations in

16 69 circuit elements), the proposed hybrid inverter circuit is simulated using OrCAD CAPTURE circuit simulation tool. The simulation performance of the hybrid inverter is discussed in the following section Bias point analysis In order to verify the functionality of a logic gate, the hybrid inverter circuit of Fig.4.10 is simulated using bias point analysis procedure explained in APPENDIX-A with a current source of. The simulation results of the circuit for different input logic conditions are summarized in Table4.5. From the Table4.5, It may be seen that for all input logic conditions, the simulated output values are within the defined logic values. It is also found that the simulation results are in good Table4.5 Summary of simulation results of a hybrid inverter Electrical input Vi (V) Electrical output Vo (V) Optical output Io (ma) Optical input Ii (ma) Electrical output Vo (V) Optical output Io (ma) agreement with the experimental values given in Table Transfer characteristics The DC sweep analysis causes to sweep a source (voltage or current), through a range of values. The electrical input voltage is swept from to 5V and its effect on the electrical optical output logic levels is studied using the DC sweep analysis and the corresponding simulation results are shown in Fig.4.13 along with tolerable electrical logic levels and noise margins. Similarly, the source LED current (IF) is varied by sweeping the voltage source (V1) in the hybrid inverter circuit and its effect on electrical and optical output is also studied using the DC sweep analysis procedure explained in APPENDIX-A The corresponding

17 70 simulation results are shown in Fig.4.14 along with tolerable optical logic levels and noise margins. 5. V OH = 4.578V NM L = V IL V OL = 0.384V NM H = V OH V IH = 3.778V V OL = 0.211V V o 0.5V V V V 5. V IL = 0.595V V i V IH = 0.8V Fig.4.13 Simulated VTC of hybrid inverter.

18 71 I OH = mA 6mA ONM L = I IL I OL = 3.812mA ONM H = I OH I IH =3.174mA 4mA 2mA I OL= 0.885mA I o I i (ma) I IL = 4.697mA I IH = 6.2mA Fig.4.14 Simulated CTC of hybrid inverter Transient response To calculate the minimum input pulse width that can be applied for obtaining undistorted output response, the input pulse width (PW) is varied in steps and the output response of the hybrid inverter is obtained using transient response analysis procedure explained in APPENDIX-A The transient response analysis causes the response of the circuit to be calculated from TIME = 0 to a specified time. Pulse source is used for transient analysis of the hybrid inverter. The general form of pulse source is PULSE (V1 V2 td tr tf PW PER), where, V1 and V2 must be specified by the user and can be either voltages and currents, td is delay time, tr is rise time, tf is fall time, PW is pulse width and PER is period. The pulse width of electrical input voltage (Vi) of hybrid inverter is varied from 10ms to 1µs and the corresponding output response is shown from Fig.4.15 to Fig.4.17.

19 72 5. Io Vo Vi 5. 5mA 0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms Fig.4.15 Transient response of hybrid inverter with electrical input PULSE ( 5V 0ns 10ns 10ns 10ms 20ms). Time 5. Vo Vi 5. Io 5mA 0s 5µs 10µs 15µs 20µs 25µs 30µs 35µs 40µs Fig.4.16 Transient response of hybrid inverter with electrical input PULSE ( 5V 0ns 10ns 10ns 10µs 20µs). Time

20 73 5. Io Vo Vi V 8.6mA 5mA 0s 0.5µs 1.0µs 1.5µs 2.0µs 2.5µs 3.0µs 3.5µs 4.0µs Fig.4.17 Transient response of hybrid inverter with electrical input PULSE ( 5V 0ns 10ns 10ns 1µs 2µs). Time It is observed that the output logic levels are with in the defined logic levels as long as the electrical input pulse width is greater than 1.4µs. Hence, the minimum electrical input pulse width that can be applied to the inverter is 1.4µs. Similarly, for optical input the minimum pulse width is observed at 1.6us and a typical case is shown in Fig.4.20.

21 74 20mA Io Ii 5mA 5. Vo 0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms Fig.4.18 Transient response of hybrid inverter with optical input PULSE (0mA 0ns 10ns 10ns 10ms 20ms). Time 20mA Ii Vo Io 5mA 5. 0s 5µs 10µs 15µs 20µs 25µs 30µs 35µs 40µs Fig.4.19 Transient response of hybrid inverter with optical input PULSE(0mA 0ns 10ns 10ns 10µs 20µs). Time

22 75 20mA Vo Io Ii 5mA 5. 0s 0.5µs 1.0µs 1.5µs 2.0µs 2.5µs 3.0µs 3.5µs 4.0µs Fig.4.20 Transient response of hybrid inverter with optical input PULSE (0mA 0ns 10ns 10ns 1µs 2µs). Time In the proposed hybrid inverter circuit, the input and output logic levels are almost the same and are within the defined logic levels. Hence, it can be used for building cascadable hybrid logic circuits. By modifying the hybrid inverter circuit, the universal hybrid NOR and hybrid NAND logic gates have been constructed and discussed in following sections. 4.5 UNIVERSAL HYBRID NOR GATE Circuit diagram of hybrid NOR gate, its principle of operation, experimental results and the transient response have been discussed in the following sections Circuit diagram of hybrid NOR gate Hybrid NOR gate has been implemented by modifying the hybrid inverter circuit by incorporating another parallel branch of phototransistor (PT2) as shown in Fig The hybrid NOR gate consists of two phototransistors (PT1 and PT2) which are connected in parallel with a load consisting of a Load LED to provide optical output and a series resistor RL across which electrical output is taken. The phototransistors will be used as switches, which can be operated with either electrical or optical input signals. The input to the photo

23 76 transistors is either electrical voltage applied to the base or the light generated due to the current flowing through the source LED and coupled to the phototransistors. The source LED and the phototransistor are obtained using 4N32 optocoupler. The Load LED is also obtained from another 4N32 optocoupler, making sure that source LED and Load LED are identical. The current source is implemented using BC558A transistor. In this circuit, Vi1 and Vi2 are the electrical inputs and Ii1 and Ii2 are the optical inputs (current through source LED s). VD1 and VD2 are the supply voltages of source LED s. Vo is the electrical output and Io (current through Load LED) is the optical output. V EE 87KΩ Current Source I = 386Ω V D1 I i1 386Ω V D2 I i2 Load LED Light Output source LED PT1 source LED PT2 I o VO 500 Ω R L V i1 V i2 Fig.4.21 Circuit diagram of Hybrid NOR gate Principle of operation When both the electrical inputs Vi1 and Vi2 to the hybrid NOR gate are at logic LOW, both the phototransistors does not conduct and most of the current from the current source flows through the Load LED and load resistance RL, producing a sufficiently large light intensity corresponding to optical logic HIGH. The output voltage Vo across the load resistor RL is

24 77 also high corresponding to electrical logic HIGH. Thus, when electrical logic LOW corresponding to are applied to both the inputs of hybrid NOR gate, it produces both electrical HIGH and optical HIGH. Similar is the case with the optical logic LOW inputs. When the electrical inputs, either Vi1 or Vi2 or both are at logic HIGH, either one of the phototransistors or both will be conducting. In this case, almost the entire current from the current source flows through the phototransistor(s). This ensures that almost zero or negligible current flows through the Load LED and series load resistance RL, giving rise to no electrical output and no optical output. Thus, the application of electrical HIGH corresponding to 5V to either one or both of the inputs of the hybrid NOR gate produces both electrical LOW and optical LOW outputs. Similar is the case with the application of optical logic HIGH inputs to the hybrid NOR gate Experimental results In order to verify the functionality of the hybrid NOR gate, the experiment is performed with different electrical and optical logic conditions. The performance of the hybrid NOR gate for different input logic conditions is shown in Table4.6. Table4.6 Input-Output response of hybrid NOR gate Electrical inputs Vi2 (V) Electrical output Vo (V) Optical output Io (ma) Vi1 (V) Optical inputs Ii1 (ma) Ii2 (ma) Electrical output Vo (V) Optical output Io (ma)

25 78 From Table4.6, it may be noted that when the electrical inputs either Vi1 or Vi2 or both are logic HIGH (5V), it produces an electrical output (Vo) of and optical output (Io) of 0mA. These output values corresponds to electrical logic LOW and optical logic LOW levels. When both the electrical inputs Vi1 and Vi2 are logic LOW (), it produces electrical output (Vo) of 4.8V and optical output (Io) of 9.6mA. These output values correspond to electrical logic HIGH and optical logic HIGH levels. Similarly, when the optical inputs either Ii1 or Ii2 or both are logic HIGH (), it produces an electrical output (Vo) of and optical output (Io) of 0mA which corresponds to electrical logic LOW and optical logic LOW. When both the optical inputs Ii1 and Ii2 are logic LOW (0mA), it produces electrical output (Vo) of 4.8V and optical output (Io) of 9.6mA, which corresponds to electrical logic HIGH and optical logic HIGH. From these experimental results, it may be noted that for all electrical and optical input logic combinations, the electrical and optical output measured values are within the defined logic levels. Thus, the hybrid NOR logic function is demonstrated Transient response To calculate the minimum input pulse width that can be applied, the input pulse width is varied and the transient response of the hybrid NOR has been obtained. The pulse width of one electrical input is varied from 5µs to 1µs by keeping the other input pulse width constant at 10µs and the output response for a typical cases are given in Fig.4.22 & Fig It is observed that the output response is within the tolerable logic levels as long as the electrical input pulse width is greater than 1.6µs. Hence, the minimum electrical input pulse width that can be applied to the hybrid NOR is 1.6µs. Similarly, for optical response the minimum input pulse width is observed at 1.8µs.

26 79 5. Vi1 5. Vi2 5. Io Vo 5mA 0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms Time Fig.4.22 Transient response of hybrid NOR gate for electrical inputs. 5. Vi1 5. Vi2 Vo V Io 8.6mA 5mA 0s 2µs 4µs 6µs 8µs 10µs 12µs 14µs 16µs 18µs 20µs Time Fig.4.23 Transient response of hybrid NOR gate for electrical 4.6 UNIVERSAL HYBRID NAND GATE Circuit diagram of hybrid NAND gate, its principle of operation, experimental results and the transient response have been discussed in the following section.

27 Circuit diagram of hybrid NAND gate Hybrid NAND gate has been implemented by modifying the hybrid inverter circuit by incorporating an additional series phototransistor (PT2) as shown in Fig The load consists of a Load LED to provide optical output and a series resistance RL across which the electrical output is taken. The phototransistors are used as switches, which can be operated with either electrical or optical input signals. The input to the phototransistors is either electrical voltage applied to the base or the light generated due to the current flowing through the source LED and coupled to the phototransistors. The source LED and the phototransistor are obtained using 4N32 optocoupler. The Load LED is also obtained from another 4N32 optocoupler, making sure that source LED and Load LED are identical. The current source is implemented using BC558A transistor. 386Ω source LED V D1 I i1 PT1 87KΩ VEE Current Source I= V D2 V i1 Load LED Light Output 386Ω source LED I i2 PT2 IO 500Ω R L V O V i2 Fig.4.24 Circuit diagram of hybrid NAND gate. In this circuit, Vi1 and Vi2 are the electrical inputs and Ii1 and Ii2 are the optical inputs (current through source LED s). Vo is the electrical output and Io (current through Load LED) is the optical output.

28 Principle of operation When both electrical or optical inputs to the hybrid NAND gate are at logic HIGH, both the phototransistors will conduct and most of the current from the current source flows through the phototransistors. This ensures that almost negligible amount of current flows through the Load LED giving rise to optical LOW and electrical LOW as outputs. Thus, the application of either electrical or optical logic HIGH to both the inputs of hybrid NAND gate produces electrical LOW and optical LOW as outputs. When either one or both inputs of the hybrid NAND gates are at either electrical or optical LOW logic, the phototransistor(s) does not conduct and most of the current from the current source flows through the Load LED, producing sufficiently large light intensity corresponding to optical logic HIGH. The output voltage Vo across the load resistance RL is also high corresponding to electrical logic HIGH. Thus, either electrical or optical LOW are applied to either one or both of the inputs of the hybrid NAND gate, produces both electrical HIGH and optical HIGH outputs Experimental results In order to verify the functionality of the hybrid NAND gate, the experiment is performed with different electrical and optical logic conditions. The performance of the hybrid NAND gate for different input logic conditions is shown in Table4.7. Table4.7 Input-Output response of hybrid NAND gate Electrical inputs Vi2 (V) Electrical output Vo (V) Optical output Io (ma) Vi1 (V) Optical inputs Electrical output Optical output Ii1 (ma) Ii2 (ma) Vo (V) Io (ma)

29 82 From the Table4.7, it may be noted that, when the electrical inputs either Vi1 or Vi2 or both are logic LOW, it produces both electrical HIGH and optical HIGH as outputs. When both the electrical inputs Vi1 and Vi2 are HIGH, it produces electrical LOW and optical LOW as outputs. Similarly, when the Optical inputs either Ii1 or Ii2 or both are LOW, it produces both electrical HIGH and optical HIGH as outputs. When both the optical inputs Ii1 and Ii2 are HIGH, it produces electrical LOW and optical LOW as outputs. From Table4.7, it may be seen that for all input conditions, the output values are within the defined logic values. Thus, the hybrid NAND logic function is demonstrated Transient response To calculate the minimum input pulse width that can be applied for obtaining undistorted output response, the input pulse width) is varied and the output response of the hybrid NAND has been measured. The pulse width of the electrical input signals are varied from 10ms to 1µs and the output response for a typical case is given in Fig Vi1 5. Vi2 5. Io Vo 5mA 0s 10µs 20µs 30µs 40µs 50µs 60µs 70µs 80µs Fig.4.25 Transient response of hybrid NAND gate for electrical inputs. Time

30 83 It is observed that the output response is within the defined logic levels as long as the electrical input pulse width is greater than 1.7µs. Hence, the minimum input pulse width that can be applied to the hybrid NAND is 1.7µs. The optical response for a typical case is given in Fig.4.26 and the minimum optical pulse width is observed at 1.5µs. 20mA Vo Io Ii2 Ii1 20mA 8.6 ma 5mA V 0s 2µs 4µs 6µs 8µs 10µs 12µs 14µs 16µs 18µs 20µs Fig.4.26 Transient response of hybrid NAND gates for optical inputs input hybrid NAND gate Time The circuit diagram of 3-input hybrid NAND gate is shown in Fig This 3-input hybrid NAND gate is obtained from 2-input hybrid NAND gate by incorporating an additional phototransistor (PT3) in series with the PT1 and PT2. The phototransistors are used as switches, which can be operated with either electrical or optical input signals. The input to the phototransistors is either electrical voltage applied to the base or the light generated due to the current flowing through the source LED and coupled to the phototransistors. The load consists of a Load LED to provide optical output and a series resistance RL across which the electrical output is taken. The current source is implemented using BC558A transistor. In this circuit, Vi1, Vi2 and Vi3 are the electrical inputs

31 84 and Ii1, Ii2 and Ii3 are the optical inputs (current through source LED s). VD1, VD2 and VD3 are the supply voltages of source LED s. Vo is the electrical output and Io (current through Load LED) is the optical output. V EE 386Ω source LED1 V D1 Ii1 PT1 Current Source R B 87KΩ Load LED Io R B1 V i1 386Ω V D2 Ii2 R L 500Ω V o source LED2 PT2 R B2 V i2 386Ω V D3 I i3 source LED3 PT3 R B3 V i3 Fig.4.27 Circuit diagram of 3-input hybrid NAND gate. To verify the functionality of the 3-input NAND, the circuit is simulated and the transient responses are shown from Fig.4.28 to Fig From the transient response, it may be noted that the hybrid NAND gate produces electrical LOW and optical LOW at the output if and only if all the three electrical or optical inputs are HIGH, otherwise it produces electrical HIGH and optical HIGH. Thus, the functionality of 3- input hybrid NAND gate is demonstrated. Fig.4.28 shows the transient response of the hybrid NAND for all electrical inputs (Vi1,Vi2,Vi3). Similarly, Fig.4.29 gives the transient response of the hybrid NAND for all

32 85 optical inputs (Ii1,Ii2,Ii3). Further, it may be noted from the Fig.4.30 that one can also apply optical (Ii1) and electrical (Vi2,Vi3) input combinations. Vi Vi2 Io Vo Vi mA 0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms Fig.4.28 Transient response of 3-input NAND gate for electrical inputs. Time 20mA Io Ii 3 Ii 2 Ii1 Vo 20mA 20mA 5mA 5. 0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms Time Fig.4.29 Transient response of 3-input NAND gate for optical inputs.

33 86 20mA Ii 5. Io Vo Vi3 Vi mA 0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms Time Fig.4.30 Transient response of 3-input NAND gate for optical (Ii1) and electrical (Vi2, Vi3) input combinations. 4.7 HYBRID OR GATE Two approaches have been discussed for implementing hybrid OR gate. In the first approach, the hybrid OR gate is implemented by cascading the universal hybrid NOR and hybrid inverter. In the second approach, the hybrid OR is implemented using alternate circuit topology, where a voltage source is used instead of a current source as the source of power for the circuit. In the following sections, both the approaches have been discussed Implementation of hybrid OR using universal hybrid NOR gate Hybrid OR logic gate has been implemented by cascading a universal hybrid NOR circuit and a hybrid inverter circuit i.e., the output of the NOR circuit is connected to the input of the inverter as shown in Fig Either the electrical output Vo1 or the optical output (LED output) of the NOR gate can be applied to the input of the hybrid inverter. In this circuit, the electrical output Vo1 of the NOR gate is coupled to the input of the inverter.

34 87 V EE V EE 87KΩ Current Source 87KΩ Current Source I = I = 386Ω source LED V D1 I i1 PT1 386Ω source LED V D2 I i2 PT2 I o1 R L1 LED PT3 500Ω Vo1 Load LED I o R L Light Output Vo1 500Ω Vi1 Vi2 hybrid NOR gate hybrid inverter Fig.4.31 Implementation of hybrid OR gate using universal NOR gate. To verify the hybrid OR logic function, the experiment is performed for different input logic conditions. Table4.8 shows the input-output response of hybrid OR gate. From Table4.8, it may be seen that the output is high, if one of the input or both the inputs are high. Thus, the hybrid OR logic function is demonstrated using universal hybrid NOR gate and hybrid NOT gate. Table4.8 Input-Output response of hybrid OR gate Electrical inputs Vi2 (V) Electrical output Vo (V) Optical output Io (ma) Vi1 (V) Optical inputs Ii1 (ma) Ii2 (ma) Electrical output Vo (V) Optical output Io (ma)

35 Transient response To calculate the minimum input pulse width that can be applied, the pulse width of the electrical input voltage (Vi) is varied from 10ms to 1µs and the corresponding output response is given in Fig It is observed that the output logic levels are with in the defined logic levels as long as the electrical input pulse width is greater than 1.3µs. Hence, the minimum input pulse width that can be applied to the hybrid OR gate is 1.3µs. It is also observe that the output logic levels are satisfied for all the input logic conditions. 5. Vo Vi2 Vi Io 5mA 0s 5µs 10µs 15µs 20µs 25µs 30µs 35µs 40µs Time Fig.4.32 Transient response of hybrid OR gate for electrical inputs. Similarly the pulse width of the optical input (Ii) is varied from 10ms to 1µs and the corresponding output response is given in Fig It is observed that the optical output logic levels are with in the defined logic levels as long as the electrical input pulse width is greater than 1.4µs. Hence, the minimum input pulse width that can be applied to the hybrid OR gate is 1.4µs.

36 89 20mA Ii1 20mA Ii 2 Io 5mA 5. Vo 0s 5µs 10µs 15µs 20µs 25µs 30µs 35µs 40µs 45µs 50µs 55µs 60µs Fig.4.33 Transient response of hybrid OR gate for optical inputs Implementation of hybrid OR gate using alternate circuit topology In the previous section, implementation of hybrid OR gate using universal hybrid NOR gate has been explained. In this section, implementation of hybrid OR gate using a alternate circuit topology is explained. Time Principle of operation The circuit diagram of the hybrid OR gate is shown in Fig It consists of two phototransistors PT1 and PT2 which are paralleled at their collector and emitter terminals. The phototransistors are used as switches which can be operated either with electrical or optical input signals with proper biasing of the base terminal. The load consists of an LED to provide optical output and a series resistor RL across which electrical output is taken. In this circuit, Vi1 and Vi2 are the electrical inputs and Ii1 and Ii2 (current through source LED s) are the optical inputs. Vo is the electrical output and Io is the optical output (current through Load LED) of the gate.

37 90 VCC = 5V V D2 V D1 386Ω I i1 I i2 386Ω source LED1 PT1 PT2 source LED2 R B1 Vi1 I o Load LED V o V i2 R B2 R L 325Ω Fig.4.34 Circuit diagram of hybrid OR gate using alternate circuit topology. When the electrical inputs either Vi1 or Vi2 or both are HIGH, it produces both electrical HIGH and optical HIGH as outputs. When both the electrical inputs Vi1 and Vi2 are LOW, it produces electrical LOW and optical LOW as outputs. When the Optical inputs either Ii1 or Ii2 or both are HIGH, it produces both electrical HIGH and optical HIGH as outputs. When both the optical inputs Ii1 and Ii2 are LOW, it produces electrical LOW and optical LOW as outputs. The hybrid OR circuit is implemented using phototransistors and LEDs from optocouplers. It is found from the characteristics that a current of flowing through the LED produces acceptable light intensity. The voltage drop across the LED is around 1.15V for producing a current of. It is found from the characteristics that a saturation collector current of flows through the phototransistor for an LED current of in the optocoupler. By adjusting the load resistor RL, a load current of is obtained which makes the phototransistor to get into the linear region. The value of VCE under this condition is found to be

38 91 0.6V. Therefore, for the phototransistor to support of collector current, a VCE of 0.6V is needed. For a supply voltage of 5V, collector emitter voltage of 0.6V for phototransistor, and a voltage drop of 1.15V across Load LED, the value of load resistor RL to provide the load current of, is found to be 325Ω. Note that LEDs from identical optocouplers are used at the input (source LED s) as well as at the output (Load LED) Experimental results To verify the hybrid OR logic function, the experiment is performed for the defined logic levels. Table4.9 shows the input-output response of hybrid OR gate. From Table4.9, it may be seen that for all input logic conditions, the output values measured are within the defined logic values. Thus, the hybrid OR logic function is demonstrated. Table4.9 Input-Output response of hybrid OR gate Electrical inputs Vi2 (V) Electrical output Vo (V) Optical output Io (ma) Vi1 (V) Optical inputs Ii1 (ma) Ii2 (ma) Electrical output Vo (V) Optical output Io (ma) Discussion of results From the Table4.9, it is clear that the optical output logic values obtained are almost the same as the optical input logic values and these values do not provide any problem in driving the stages that follow. The electrical output corresponding to logic HIGH is only 3.15V which is not within the defined logic HIGH level. This value is not enough to drive the next stage. To use the hybrid OR gate in cascadable systems,

39 92 the electrical output corresponding to logic HIGH is to be boosted to 5V. This can be achieved by incorporating two stages of inversion using transistors Q1 and Q2 in the Hybrid OR circuit of Fig The modified hybrid OR circuit is shown in Fig The performance of this hybrid OR gate for different input logic conditions is shown in Table4.10. From the Table4.10, it may be seen that the electrical output level corresponding to logic HIGH is the same as that of electrical input HIGH i.e., 5V. But this modified hybrid OR gate is not suitable to use in building larger cascadable hybrid systems because of additional buffer stage requirement to drive the stages that follow. V CC = 5V V D2 V D1 386 Ω 386Ω I i1 I i2 source LED1 PT1 PT2 source LED2 Load LED 5V V i2 V i1 I o 220Ω V o R 330Ω V o 330Ω Q1 Q2 325 Ω Fig.4.35 Circuit diagram of modified hybrid OR gate.

40 93 Table4.10 Input-Output response of modified hybrid OR gate Electrical inputs Electrical output Optical output Vi1 (V) Vi2 (V) Vo (V) Io (ma) Optical inputs Ii1 (ma) Ii2 (ma) Electrical output Vo (V) Optical output Io (ma) Comparison of the two approaches Implementation of hybrid OR gate using first approach i.e., using universal hybrid NOR and inverter needs three phototransistors and two electrical transistors. Implementation of hybrid OR gate using alternate circuit topology requires only two phototransistors and two electrical transistors. The first approach is preferable from the point of cascadability than the second one. 4.8 HYBRID AND GATE Two approaches have been discussed for implementing hybrid AND gate. In the first approach, the hybrid AND gate is implemented by cascading the universal hybrid NAND gate and hybrid inverter. In the second approach, the hybrid AND gate is implemented using alternate circuit topology, where a voltage source is used instead of a current source as the source of power for the circuit. In the following sections, both the approaches have been discussed and compared Implementation of hybrid AND gate using universal hybrid NAND gate Hybrid AND gate can be obtained by cascading a universal hybrid NAND gate and a hybrid NOT gate i.e., the output of the NAND circuit is connected to the input of the NOT as shown in Fig Either the

41 94 electrical output Vo1 or the optical output (LED output) of the hybrid NAND gate can be applied to the input of the NOT gate. In this circuit, the electrical output Vo1 of the hybrid NAND gate is coupled to the input of the NOT gate. To verify the hybrid AND logic function, the experiment is performed for different input logic conditions. Table4.11 shows the inputoutput response of hybrid AND gate. From the Table4.11, it may be seen that the output is HIGH, if and only if both the inputs are HIGH. Thus, the hybrid AND logic function is demonstrated using a universal hybrid NAND gate and hybrid NOT gate. V EE V EE 386Ω source LED V D1 I i1 PT1 87KΩ Current Source I = LED 87KΩ Current Source I = 386Ω source LED V D2 I i2 V i1 PT2 I o1 R L1 Vo1 500Ω PT3 Load LED Io R L Light output V O 500Ω V i2 hybrid NAND gate hybrid inverter Fig.4.36 Implementation of hybrid AND using universal NAND gate.

42 95 Table4.11 Input-Output response of hybrid AND gate Electrical inputs Vi2 (V) Electrical output Vo (V) Optical output Io (ma) Vi1 (V) Optical inputs Ii1 (ma) Ii2 (ma) Electrical output Vo (V) Optical output Io (ma) Transient response To calculate the minimum input pulse width that can be applied for obtaining undistorted output response, the input pulse width (PW) is varied in steps and the output response of the hybrid AND gate has been obtained. The pulse width of the electrical input signals is varied from 1ms to 1µs and the output response for a typical case is given in Fig Vi1 5. V(Vi2) 5. V(Vo) Io(mA) 5mA 0s 10ms 20ms 30ms 40ms 50ms 60ms 70ms 80ms Time Fig.4.37 Transient response of hybrid AND gate for electrical inputs.

43 96 It is observed that the output response is not distorted as long as the electrical input pulse width is greater than 1.4µs. Hence, the minimum input pulse width that can be applied to the hybrid AND is 1.4µs. The optical response for a typical case is given in Fig.4.38 and the minimum optical input pulse width is observed at 1.3µs. 20mA Ii(mA) 20mA Ii(mA) Io(mA) 5mA 5. V(Vo) 0s 10ms 20ms 30ms 40ms 50ms 60ms 70ms 80ms Time Fig.4.38 Transient response of hybrid AND gate for optical inputs Implementation of hybrid AND gate using alternate circuit topology In the previous section, realization of hybrid AND gate using universal hybrid NAND gate has been explained. In this section, implementation of hybrid AND gate using alternate circuit topology is explained Principle of operation The circuit diagram of the hybrid AND logic gate is shown in Fig.4.39.The circuit consists of two phototransistors (PT1 and PT2), a LED and a resistor RL connected in series serve as load to provide optical and electrical outputs. Vi1 and Vi2 are the electrical inputs and Ii1 and Ii2 are the optical inputs (current through source LED s) of the logic gate. Vo is

44 97 the electrical output and Io is the optical output (current through Load LED) of the logic gate. V CC = 5V V D1 386Ω I i1 source LED1 PT1 V i1 386Ω I i2 source LED2 V D2 PT2 V i2 Load LED I o R L V o R Fig.4.39 Circuit diagram of hybrid AND gate using alternate circuit topology. When any of the electrical inputs or both the inputs are LOW, the AND gate produces an electrical LOW and an optical LOW as a output. When both the electrical inputs Vi1 and Vi2 are HIGH, it produces logic HIGH at electrical and optical output. When the optical inputs either Ii1 or Ii2 or both are LOW, it produces both electrical LOW and optical LOW as outputs. When both the optical inputs Ii1 and Ii2 are HIGH, it produces electrical HIGH and optical HIGH as outputs. The hybrid AND circuit is implemented using phototransistors and LEDs from optocouplers. It is found from the characteristics that a current of flowing through the LED produces acceptable light intensity. The voltage drop across the Load LED is around 1.15V for

45 98 producing a current of. It is found from the characteristics of a phototransistor that a saturation collector current of more than flows through the phototransistor for a LED current of in the optocoupler. By adjusting the load resistor RL, a collector current of is obtained which makes the phototransistor to get into the linear region. The value of VCE under this condition is found to be 0.6V. Therefore, for the phototransistor to support of collector current, a VCE of 0.6V is needed. For a supply voltage of 5V, collector emitter voltage of 0.6V for each phototransistor, and a voltage drop of 1.15V across LED, the value of load resistor RL to provide the load current of, is found to be 265Ω Experimental Results To verify the hybrid AND logic function, the experiment is performed for different electrical/optical logic values. Table4.12 shows the input-output response of hybrid AND gate. Table4.12 Input-Output response of hybrid AND gate Electrical inputs Electrical output Vo (V) Optical output Io (ma) Vi1 (V) Vi2 (V) Ii1 (ma) Optical inputs Ii2 (ma) Electrical output Vo (V) Optical output Io (ma)

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