BiCMOS Logic Gates. University of Connecticut 224

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1 BiCMOS Logic Gates University of Connecticut 224

2 BiCMOS - Best of Both Worlds? CMOS circuitry exhibits very low power dissipation, but Bipolar logic achieves higher speed and current drive capability. BiCMOS achieves low standby dissipation like CMOS, but high speed and current drive capability like TTL and ECL. The disadvantage of BiCMOS is fabrication complexity (up to 30 masking steps, compared to about 20 for bipolar logic or CMOS). This translates into higher cost and longer design cycles. $ Notable examples of the BiCMOS technology are the Intel P6 (a.k.a. Pentium Pro) which appeared in 1996, and its successor the P7. University of Connecticut 225

3 BiCMOS Inverter P 1 N 3 Q P P 1 and N 1 perform the logic function. Q P and Q O are lowimpedance output drivers. N 2 and N 3 remove base charge from the bipolar transistors during switching. N 1 Q O N 2 University of Connecticut 226

4 BiCMOS Inverter 0. P 1 N 3 Q P N 1 Q O. N 2 University of Connecticut 227

5 BiCMOS Inverter VTC CMOS BiCMOS The BiCMOS inverter shown here exhibits reduced logic swing ( - 2V BEA ) compared to CMOS ( ). Reduction of the supply voltage will make this problem more severe V DD 3. 3V K 40µ A / V V 1V β F 50 V 0. 7V BEA 2 T University of Connecticut 228

6 BiCMOS NAND Gate With both inputs high: P A P B Q P N B3 N A3 With V A high, V B low: V B N B1 V A N A1 Q O N 2 University of Connecticut 229

7 How Fast is BICMOS? P 1 N 3 Q P For highly-capacitive off-chip loads, fast switching is possible due to the high current driving capability of the bipolar transistors. The speed is limited by the parasitic capacitances of the Q P, which must be driven by the P 1 - N 3 CMOS circuit. N 1 Q O For on-chip loads presenting very little capacitance, BiCMOS offers no advantage if N 2 C L < C BCP BiCMOS integrated circuits are really CMOS on the inside! University of Connecticut 230

8 BiCMOS Applications Modern BiCMOS, invented by Intel, hit the market in Ever-increasing clock frequencies on motherboards of PC s and workstations may require that the VLSI / ULSI chips be made in BiCMOS. (Witness the Intel, AMD, and Cyrix µp chips.) Central Processing Units (CPU s) of minisupercomputers can be implemented in BiCMOS, with packing density and dissipation advantages over ECL. (e.g., the Cray Research Baby Cray J916 Computer) TTL will soldier on in motherboard SSI and MSI applications, where BiCMOS does not boast an advantage. But the BiCMOS party may be over when supply voltages drop below 1.8 V. BJT s have a fixed turn-on voltage; MOSFET thresholds can be reduced to at least 0.3V for room temperature operation. University of Connecticut 231

9 The Problem with BiCMOS For standard BiCMOS, the logic swing is - 2V BEA. Supply voltages are continually being reduced, because P C V L 2 DD When is reduced to 1.8V, standard BiCMOS will provide a logic swing of only 0.4V; this isn t acceptable! We can provide shunt elements which increase the voltage swing of BiCMOS, but Turning off the BJT s isn t the answer! If the supply voltage is 1.8V, the BJT s can only conduct for 0. 7V V 11. V In this case the BJT s can not effectively boost the switching speed. University of Connecticut 232 OUT

10 Full-Rail BiCMOS Inverter w/ Resistive Shunts P 1 N 1 R 1 R 2 Q P Q O This BiCMOS design provides a rail-to-rail voltage swing. For < V BEA, N 1 and R 2 conduct, bringing V OL all the way to 0. For V BEA < < - V BEA, one or both BJT s conducts. For - V BEA <, P 1 and R 1 conduct, bringing V OH all the way to. It is not practical to fabricate this circuit with resistors, but a similar circuit can be made using an active shunt for Q O. University of Connecticut 233

11 BiCMOS Inverter w/ Active Shunt P 1 N 1 Q P N 3 Q O This BiCMOS design provides a voltage swing of - V BEA. For < V BEA, N 3 and N 2 conduct, bringing V OL all the way to 0. For V BEA < < - V BEA, one or both BJT s conducts. The base-emitter junction of Q P is not shunted, so V OH - V BEA. N 2 University of Connecticut 234

12 Full Rail BiCMOS Inverter w/ Paralleled CMOS Output P 1 N 3 N 1 Q P Q O N 2 P O The parallel CMOS inverter provides rail-to-rail operation. For < V BEA, N O conducts, bringing V OL all the way to 0. For V BEA < < - V BEA, one or both BJT s conducts. For - V BEA <, P O conducts, bringing V OH all the way to. N O University of Connecticut 235

13 Buffered CMOS University of Connecticut 236

14 CMOS - Single Stage 1.8V V T -0.6V 2.2µ m/ 0.5µ m V T 0.6V 0.9µ m/ 0.5µ m C L t k k OX ' P ' N 100 Angstroms 80µ A/ V 2 200µ A/ V 2 t P A University of Connecticut 237

15 CMOS - Single Stage / 50pF 1.8V V T -0.6V 2.2µ m/ 0.5µ m V T 0.6V 0.9µ m/ 0.5µ m 50pF K K P N t P University of Connecticut 238

16 CMOS - Three Stages / 50pF 1.8V 2.2/ / / / / / pF K C t 1 L1 P1 K C t 2 L2 P2 K C t 3 L3 P3 t P University of Connecticut 239

17 CMOS - Six Stages / 50pF 1.8V 2.2/ / / / / / 0.5 WIRED TO THE NEXT PAGE! K C t 1 L1 P1 K C t 2 L2 P2 K C t 3 L3 P3 University of Connecticut 240

18 CMOS - Six Stages / 50pF 1.8V 275/ / / 0.5 K C t 4 WIRED FROM THE PREVIOUS PAGE! L4 P4 110/ 0.5 K C t 5 L5 P5 550/ 0.5 K C t 6 L6 P6 2750/ pF t P University of Connecticut 241

19 GaAs Direct-Coupled FET Logic (DCFL) University of Connecticut 242

20 DCFL Inverter DCFL gates are similar to NMOS circuits, but are implemented with GaAs MESFET s rather than Si MOSFET s. The advantage of DCFL is speed - it is up to 3 times faster than CMOS. The disadvantages of DCFL are fabrication complexity and cost. GaAs 75 mm wafer - $100 Si 200 mm wafer - $10 Si 300 mm wafers - coming soon! GaAs technology is less established compared to Si technology, and the fabrication of enhancement type MESFET s is difficult. University of Connecticut 243

21 DCFL Inverter - Basic Operation LOW. N L N O HIGH. University of Connecticut 244

22 DCFL NOR Gate V A V B V OL. N L V A N OA V B N OB V A or V B. DCFL NAND gates are not practical due to restrictions imposed on, V OL, and the enhancement device threshold voltages. University of Connecticut 245

23 Buffered DCFL NOR Gate V A V B V A V B The added source follower provides a low-impedance output driver for off-chip loads. University of Connecticut 246

24 DCFL Characteristics Compare the 1999 state-of-the art for GaAs DCFL and Si CMOS: GaAs DCFL vs. Si CMOS: 0.25 µm technology propagation delay dissipation SRAM embedded in VLSI GaAs DCFL 35 ps 30 µw (DC) 32 kb Si CMOS 75 ps 1 µw / MHz 128 kb GaAs exhibits higher electron mobility than Si. Due to the GaAs electron velocity characteristic, DCFL can operate at a reduced supply voltage without a penalty in switching speed. University of Connecticut 247

25 DCFL Applications For a given minimum linewidth, GaAs DCFL circuitry is about 2 to 3 times faster than Si CMOS because of the difference in electron mobilities. The extra speed comes at a premium, because GaAs technology is less developed and DCFL is expensive. DCFL applications are at the high end, where the extra cost can be justified. Examples are the Cray Y-MP and the Vitesse Semiconductor GaAs microprocessor, which boasts 1.2 M transistors [see Ira Deyhimy, Gallium Arsenide Joins the Giants, IEEE Spectrum, pp , February 1995]. At the present time, the area of fastest growth for GaAs DCFL is communications. A factor of three isn t much, though, when you consider the rapid advancement of Si CMOS / BiCMOS technology. University of Connecticut 248

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