High-Speed, 5 V, 0.1 F CMOS RS-232 Drivers/Receivers ADM222/ADM232A/ADM242

Transcription

1 a FEATURES 200 kb/s Transmission Rate Small (0. F) Charge Pump Capacitors Single V Power Supply Meets All EIA-232-E and V.2 Specifications Two Drivers and Two Receivers On-Board DC-DC Converters V Output Swing with V Supply 30 V Receiver Input Levels Pin Compatible with 222/232A/242 APPLICATIONS Computers Peripherals Modems Printers Instruments GENERAL DESCRIPTION The ADM222, ADM232A, ADM242 are a family of high-speed line drivers/receivers offering transmission rates up to 200 kb/s. Operating from a single V power supply, a highly efficient on-chip charge pump using small (0. µf) external capacitors allows bipolar levels to be developed. Two drivers and two receivers are provided on each device. The devices are fabricated on BiCMOS, an advanced mixed technology process that combines low power CMOS with highspeed bipolar circuitry. This allows for transmission rates up to 200 kb/s, yet minimizes the quiescent power supply current to under ma. The ADM232A is a pin-compatible, high-speed upgrade for the AD232 and for the ADM232L. It is available in 6-lead DIP and in both narrow and wide surface-mount (SOIC) packages. The ADM222 contains an additional shutdown (SHDN) function that may be used to disable the device, thereby reducing the supply current to 0. µa. During shutdown, all transmit/receive High-Speed, V, 0. F CMOS Drivers/Receivers ADM222/ADM232A/ADM242 INPUTS* T IN T2 IN R OUT R2 OUT FUNCTIONAL BLOCK DIAGRAM C+ +V TO +0V VOLTAGE DOUBLER C C2+ +V TO 0V VOLTAGE INVERTER ADM2xx T T2 R R2 V INPUT EN SHDN T OUT R IN INPUTS** (ADM242) (ADM222, ADM242) * INTERNAL 400k PULL-UP RESISTOR ON EACH INPUT ** INTERNAL k PULL-DOWN RESISTOR ON EACH INPUT functions are disabled. The ADM222 is available in -lead DIP and in a wide surface-mount (SOIC) package. The ADM242 combines both shutdown (SHDN) and enable (EN) functions. The shutdown function reduces the supply current to 0. ma. During shutdown, the transmitters are disabled but the receivers continue to operate normally. The enable function allows the receiver outputs to be disabled thereby facilitating sharing a common bus. The ADM242 is available in -lead DIP and in a wide surface-mount (SOIC) package. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 06, Norwood, MA , U.S.A. Tel: 7/ World Wide Web Site: Fax: 7/46-33 Analog Devices, Inc., 200

2 SPECIFICATIONS ( = V 0%. C C4 = 0. F; all specifications T MIN to T unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comments TRANSMITTERS Output Voltage Swing ± ± V All Transmitter Outputs Loaded with 3 kω to Ground Input Logic Threshold Low, V INL.7 0. V T IN Input Logic Threshold High, V INH V T IN Logic Pull-Up Current 2 40 µa T IN = 0 V Data Rate 200 kb/s Output Resistance 300 Ω = = = 0 V, V OUT = ± 2 V Output Short Circuit Current (Instantaneous) ±0 ma RECEIVERS Input Voltage Range V Input Threshold Low 0..2 V Input Threshold High V Input Hysteresis V = V Input Resistance 3 7 kω T A = 0 C to C Output Voltage Low, V OL V I OUT = 3.2 ma Output Voltage High, V OH 3. V I OUT =.0 ma Output Short-Circuit Current 2 ma Source Current (V OUT = )* Output Short-Circuit Current 0 3 ma Sink Current (V OUT = )* Output Leakage Current ±0.0 ±0 µa SHDN = /EN = 0 V V OUT EN Input Threshold Low, V INL.4 0. V EN Input Threshold High, V INH V POWER SUPPLY Power Supply Current 4 ma No Load 3 ma 3 kω Load on Both Outputs Shutdown Power Supply Current 0. 0 µa SHDN Input Leakage Current ± µa SHDN Input Threshold Low, V INL.4 0. V SHDN Input Threshold High, V INH V AC CHARACTERISTICS Transition Region Slew Rate 3 30 V/µs C L = 0 pf to 000 pf, R L = 3 kω to 7 kω Measured from +3 V to 3 V or 3 V to +3 V Transmitter Propagation Delay TTL to µs t PHLT.0 3. µs t PLHT Receiver Propagation Delay to TTL µs t PHLR µs t PLHR Receiver Output Enable Time 2 00 ns t ER Receiver Output Disable Time ns t DR Transmitter Output Enable Time 20 µs SHDN Goes High Transmitter Output Disable Time 3. µs SHDN Goes Low Transmitter + to Propagation Delay Difference 0 ns Receiver + to Propagation Delay Difference 200 ns *Guaranteed by design, not production tested. Specifications subject to change without notice. 2

3 ABSOLUTE IMUM RATINGS* (T A = 2 C unless otherwise noted) V ( 0.3 V) to +3 V V to 3 V Input Voltages T IN V to ( V) R IN ± 30 V Output Voltages T OUT (, +0.3 V) to (, 0.3 V) R OUT V to ( V) Short Circuit Duration T OUT Continuous Power Dissipation N mw (Derate 7. mw/ C above 70 C) θ JA, Thermal Impedance C/W Power Dissipation R-6N mw (Derate 7 mw/ C above 70 C) θ JA, Thermal Impedance C/W Power Dissipation R-6W mw (Derate 7 mw/ C above 70 C) θ JA, Thermal Impedance CW Power Dissipation N mw (Derate 7 mw/ C above 70 C) θ JA, Thermal Impedance C/W Power Dissipation R-W mw (Derate 7 mw/ C above 70 C) θ JA, Thermal Impedance C/W Operating Temperature Range Industrial (A Version) C to + C Storage Temperature Range C to +0 C Lead Temperature (Soldering, 0 sec) C Vapor Phase (60 sec) C Infrared ( sec) C *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Test Circuits V IN 3V V IN 3V 0V t PLHT t PHLT V OUT 0V Figure. Transmitter Propagation Delay Timing t PHLR t PLHR V OUT 0% Figure 3. Receiver Propagation Delay Timing 3V EN INPUT 3V 0V EN INPUT 0V t DR t ER V OH 3.V V OH 0.V RECEIVER OUTPUT 0.V RECEIVER OUTPUT V OL V OL + 0.V Figure 2. Receiver Enable Timing Figure 4. Receiver Disable Timing 3

4 V IN TRANSMITTER OUTPUT SHDN 3k 0pF V OUT Figure. Shutdown Test Circuit SHDN INPUT 3V 0V t DT + V V Figure 6. Transmitter Shutdown Disable Timing INPUTS* C C2 T IN T2 IN R OUT R2 OUT C 6.3V 7 2 C+ +V TO +0V 3 4 VOLTAGE DOUBLER C C2+ +V TO 0V 7 VOLTAGE INVERTER ADM222 T T2 6 R R2 V INPUT 4 SHDN C3 C4 T OUT R IN INPUTS** * INTERNAL 400k PULL-UP RESISTOR ON EACH INPUT ** INTERNAL k PULL-DOWN RESISTOR ON EACH INPUT PIN FUNCTION DESCRIPTION Mnemonic Function Power Supply Input, V ± 0%. Internally generated positive supply (+0 V nominal). Internally generated negative supply ( 0 V nominal). Ground Pin. Must be connected to 0 V. C+ External capacitor, (+ terminal) is connected to this pin. C External capacitor, ( terminal) is connected to this pin. C2+ External capacitor 2, (+ terminal) is connected to this pin. External capacitor 2, ( terminal) is connected to this pin. T IN Transmitter (Driver) Inputs. These inputs accept levels. An internal 400 kω pull-up resistor to is connected on each input. T OUT Transmitter (Driver) Outputs. These are levels (typically ± V). R IN Receiver Inputs. These inputs accept signal levels. An internal kω pull-down resistor to is connected on each of these inputs. R OUT Receiver Outputs. These are levels. NC No Connect. No connections are required to this pin. EN (ADM242 Only) Active Low Digital Input. May be used to enable or disable (three-state) both receiver outputs. SHDN (ADM222 and ADM242) Active Low Digital Input. May be used to disable the device so that the power consumption is minimized. On the ADM222 all drivers and receivers are disabled. On the ADM242 the drivers are disabled but the receivers remain enabled. NC C+ 2 3 C 4 C ADM222 TOP VIEW (Not to Scale) SHDN 7 6 T OUT 4 R IN 3 R OUT 2 T IN T2 IN 0 R2 OUT NC = NO CONNECT Figure 7. ADM222 Typical Operating Circuit Figure. ADM222 DIP and SOIC Pin Configurations 4

5 EN SHDN C+ 6 C C C ADM232A 3 TOP VIEW (Not to Scale) 2 T OUT R IN R OUT T IN C C ADM242 TOP VIEW (Not to Scale) T OUT 4 R IN 3 R OUT 2 T IN 7 0 T2 IN T2 IN R2 OUT 0 R2 OUT Figure. ADM232A DIP/SOIC Pin Configuration Figure. ADM242 DIP/SOIC Pin Configuration V INPUT V INPUT C C2 3 4 C 6.3V 6 C+ +V TO +0V VOLTAGE DOUBLER C C2+ +V TO 0V VOLTAGE INVERTER 2 6 C3 C4 C C C 6.3V 7 C+ +V TO +0V VOLTAGE DOUBLER C C2+ +V TO 0V VOLTAGE INVERTER 3 7 C3 C4 INPUTS* T IN T2 IN 0 T T2 4 7 T OUT INPUTS* T IN T2 IN 2 T T2 T OUT R OUT R2 OUT 2 R R2 3 R IN INPUTS** R OUT R2 OUT 3 0 R R2 4 R IN INPUTS** ADM232A EN ADM242 SHDN * INTERNAL 400k PULL-UP RESISTOR ON EACH INPUT ** INTERNAL k PULL-DOWN RESISTOR ON EACH INPUT Figure 0. ADM232A Typical Operating Circuit 6 * INTERNAL 400k PULL-UP RESISTOR ON EACH INPUT ** INTERNAL k PULL-DOWN RESISTOR ON EACH INPUT Figure 2. ADM242 Typical Operating Circuit

6 Typical Performance Characteristics 0 0 Tx O/P HI, V 0 Tx O/P VOLTAGE V 0 Tx O/P LO LOAD CURRENT ma TPC. Charge Pump, vs. Current LOAD CURRENT ma TPC 4. Transmitter Output Voltage vs. Current TRANSMITTER OUTPUT VOLTAGE V kbps 230kBps kbps 460kBps 460kBps 230kBps % A4 V 0.00V V 00 s LOAD CAPACITANCE pf TPC 2. Transmitter Baud Rate vs. Load Capacitance TPC. Charge Pump, Exiting Shutdown T : 6.2V : 3.V T : 6.0V : 2.V T T CH 0.0V CH2.00V M.00 s CH2 6.4V TPC 3. Transmitter Unloaded Slew Rate CH 0.0V CH2.00V M.00 s CH2 6.4V TPC 6. Transmitter Fully Loaded Slew Rate 6

7 GENERAL INFORMATION The ADM222/ADM232A/ADM242 are high-speed drivers/receivers requiring a single digital V supply. The standard requires transmitters that will deliver ± V minimum on the transmission channel and receivers that can accept signal levels down to ± 3 V. The parts achieve this by integrating stepup voltage converters and level-shifting transmitters and receivers onto the same chip. CMOS technology is used to keep the power dissipation to an absolute minimum. All devices contain an internal charge pump voltage doubler and a voltage inverter that generates ± 0 V from the V input. Four external 0. µf capacitors are required for the internal charge pump voltage converter. The ADM222/ADM232A/ADM242 is a modification, enhancement and improvement to the AD230-AD24 family and derivatives thereof. It is essentially plug-in-compatible and does not have materially different applications. CIRCUIT DESCRIPTION The internal circuitry consists of four main sections. These are: Charge Pump Voltage Converter to Transmitters to Receivers Enable and Shutdown Functions. Charge Pump DC-DC Voltage Converter The Charge Pump Voltage converter consists of an oscillator and a switching matrix. The converter generates a ±0 V supply from the input V level. This is done in two stages using a switched capacitor technique. The V input supply is doubled to 0 V using capacitor C as the charge storage element. The 0 V level is also generated from the input V supply using C and C2 as the storage elements. Capacitors C3 and C4 are used to reduce the output ripple. Their values are not critical and can be reduced if higher levels of ripple are acceptable. The charge pump capacitors C and C2 may also be reduced at the expense of higher output impedance on the and supplies. The and supplies may also be used to power external circuitry if the current requirements are small. Please refer to the typical performance characteristics which shows the, output voltage vs. current. In the shutdown mode the charge pump is disabled and decays to while decays to 0 V. Transmitter (Driver) Section The Drivers convert input levels into output levels. With = V and driving a typical load, the output voltage swing is ± V. Even under worst-case conditions the drivers are guaranteed to meet the ± V minimum requirement. The input threshold levels are both TTL- and CMOS-compatible with the switching threshold set at /4. With a nominal = V, the switching threshold is.2 V typical. Unused inputs may be left unconnected, as an internal 400 kω pull-up resistor pulls them high forcing the outputs into a low state. As required by the standard, the slew rate is limited to less than 30 V/µs without the need for an external slew limiting capacitor, and the output impedance in the power-off state is greater than 300 Ω. Receiver Section The receivers are inverting level-shifters that accept input levels (±3 V to ± V) and translate them into V TTL/ CMOS levels. The inputs have internal kω pull-down resistors to ground and are also protected against overvoltages of up to ± 30 V. The guaranteed switching thresholds are 0. V minimum and 2.4 V maximum, which are well within the ± 3 V requirement. The low level threshold is deliberately positive as it ensures that an unconnected input will be interpreted as a low level. The receivers have Schmitt trigger input with a hysteresis level of 0. V. This ensures error-free reception for both noisy inputs and for inputs with slow transition times Enable and Shutdown Functions On the ADM222, both receivers are fully disabled during shutdown. On the ADM242, both receivers continue to operate normally. This function is useful for monitoring activity so that when it occurs, the device can be taken out of the shutdown mode. The ADM242 also contains a receiver enable function (EN) which can be used to fully disable the receivers, independent of SHDN. APPLICATIONS INFORMATION A selection of typical operating circuits is shown in TPCs 6 and Figure % A V 2.0V V s Figure 3. Transmitter Output Disable Timing 7

8 OUTLINE DIMENSIONS 0.00 (20.32) 0.70 (20.07) 0.70 (.) 0.20 (.33) 0.0 (3.) 0.30 (3.30) 0. (2.2) (0.6) 0.0 (0.46) 0.04 (0.36) (2.4) BSC (.7) (.2) 0.04 (.4) 0.20 (7.) 0.20 (6.3) (6.0) 0.0 (0.3) MIN SEATING 0.00 (0.3) MIN (.2) 0.0 (0.3) GAUGE 0.32 (.26) 0.30 (7.7) (7.62) (0.2) 0. (4.) 0.30 (3.30) 0. (2.2) 0.04 (0.36) 0.00 (0.2) 0.00 (0.20) COMPLIANT TO JEDEC STANDARDS MS-00-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 4. 6-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-6) Dimensions shown in inches and (millimeters) B 0.0 (0.434) 0.0 (0.376) (0.22) 7.40 (0.23) 0.6 (0.43) 0.00 (0.337) 0.30 (0.0) 0.0 (0.003) COPLANARITY.27 (0.000) BSC 2.6 (0.043) 2.3 (0.02) (0.020) SEATING 0.33 (0.030) 0.3 (0.022) 0.20 (0.007) (0.02) 0.2 (0.00) 4.27 (0.000) 0.40 (0.07) COMPLIANT TO JEDEC STANDARDS MS-03-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. 6-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-6) Dimensions shown in millimeters and (inches) B

9 0.00 (0.337).0 (0.3) 4.00 (0.7) 3.0 (0.46) (0.244).0 (0.223) 0.2 (0.00) 0.0 (0.003) COPLANARITY (0.000) BSC 0. (0.020) 0.3 (0.022).7 (0.06).3 (0.03) SEATING (0.00) 0.7 (0.0067) 0.0 (0.07) 0.2 (0.00).27 (0.000) 0.40 (0.07) 4 COMPLIANT TO JEDEC STANDARDS MS-02-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 6. 6-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-6) Dimensions shown in millimeters and (inches) A.7 (0.4626).3 (0.446) (0.22) 7.40 (0.23) 0.6 (0.43) 0.00 (0.337) 0.30 (0.0) 0.0 (0.003) COPLANARITY 2.6 (0.043) 2.3 (0.02) (0.020) SEATING 0.33 (0.030) (0.000) 0.3 (0.022) 0.20 (0.007) BSC (0.02) 0.2 (0.00) 4.27 (0.000) 0.40 (0.07) COMPLIANT TO JEDEC STANDARDS MS-03-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 7. -Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-) Dimensions shown in millimeters and (inches) A

10 0.20 (23.37) 0.00 (22.6) 0.0 (22.3) 0.20 (.33) 0.0 (3.) 0.30 (3.30) 0. (2.2) (0.6) 0.0 (0.46) 0.04 (0.36) 0.00 (2.4) BSC (.7) (.2) 0.04 (.4) (7.) 0.20 (6.3) (6.0) 0.0 (0.3) MIN SEATING 0.00 (0.3) MIN (.2) 0.0 (0.3) GAUGE 0.32 (.26) 0.30 (7.7) (7.62) (0.2) 0. (4.) 0.30 (3.30) 0. (2.2) 0.04 (0.36) 0.00 (0.2) 0.00 (0.20) COMPLIANT TO JEDEC STANDARDS MS-00 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure. -Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-) Dimensions shown in inches and (millimeters) A ORDERING GUIDE Model Temperature Range Package Description Package Option ADM222AN 40 C to + C -Lead PDIP N- ADM222ANZ 40 C to + C -Lead PDIP N- ADM222AR 40 C to + C -Lead SOIC_W RW- ADM222ARZ 40 C to + C -Lead SOIC_W RW- ADM222ARZ-REEL 40 C to + C -Lead SOIC_W RW- ADM232AAN 40 C to + C 6-Lead PDIP N-6 ADM232AANZ 40 C to + C 6-Lead PDIP N-6 ADM232AARN 40 C to + C 6-Lead SOIC_N R-6 ADM232AARN-REEL 40 C to + C 6-Lead SOIC_N R-6 ADM232AARN-REEL7 40 C to + C 6-Lead SOIC_N R-6 ADM232AARNZ 40 C to + C 6-Lead SOIC_N R-6 ADM232AARNZ-REEL 40 C to + C 6-Lead SOIC_N R-6 ADM232AARNZ-REEL7 40 C to + C 6-Lead SOIC_N R-6 ADM232AARW 40 C to + C 6-Lead SOIC_W RW-6 ADM232AARW-REEL 40 C to + C 6-Lead SOIC_W RW-6 ADM232AARWZ 40 C to + C 6-Lead SOIC_W RW-6 ADM232AARWZ-REEL 40 C to + C 6-Lead SOIC_W RW-6 ADM242AN 40 C to + C -Lead PDIP N- ADM242ANZ 40 C to + C -Lead PDIP N- ADM242AR 40 C to + C -Lead SOIC_W RW- ADM242AR-REEL 40 C to + C -Lead SOIC_W RW- ADM242ARZ 40 C to + C -Lead SOIC_W RW- ADM242ARZ-REEL 40 C to + C -Lead SOIC_W RW- Z = RoHS Compliant Part. 0

11 REVISION HISTORY /0 Rev. A to Rev. B Updated Outline Dimensions... Changes to Ordering Guide Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D023-0-/0(B)