Topics VLSI SIGNAL PROCESSING CHAPTER 2

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1 VLSI SIGNAL PROCESSING CHAPER Basics of Synchronous Design opics Description of signal-processg algorithms: signal-flow graph (also called data-flow graph). Implementation methods: one-to-one mappg function multiplexg time foldg Selection/adaptation by: Sabih Gerez, University of wente, March, 4 Selection/adaptation by: Sabih Gerez, University of wente, March, 4 y[n] = x[n].5 y[(n-)] -.5 y[(n-)] = samplg period n=,,, x() DDG = data dependency graph y() node = function (, puts) edge = data dependency /puts represented by source/sk c delay functions z - when is SFG legal? no loops with delay x() x(f) y() y(f) Selection/adaptation by: Sabih Gerez, University of wente, March, 4 c.5.5 x() y() z - f s y(f-) z - f s y(f-) c SFG = signal flow graph Functional languages : a textual representation of an SFG goal = to expla SFG semantics. Basic element = a signal = ordered sequence of values time s = a b means s [ f ] = a [ f ] b [ f ] for f refers to signals of previous frames n means x [ f - n ] e.g. b = b@ a means b [ f ] = b [ f - ] a [ f ] for f =... Selection/adaptation by: Sabih Gerez, University of wente, March, 4 4 b[] a[] b[] a[] b[] a[] b[] a[] s[] s[] s[] s[] a[] a[] a[] a[] b[] b[] b[] b[]

2 Functional languages : a textual representation of an SFG. Algorithms are concurrent function applications. Sgle assignment => he order of the statements is irrelevant. Inputs are available at the begng of the frame. Outputs are available at the end of the frame. Functional languages : a textual representation of an SFG 4. Loops (other than time loop) are possible s [ ] = ( i :.. ) : : short hand notation s [ i ] = s [ i ] a [ i ] s [ ] = s [ ] = s [ ] a [ ] s [ ] = s [ ] a [ ] s [ ] = s [ ] a [ ] ime loop iterator f not shown explicitly! loop boundaries are manifest = known at compile time Selection/adaptation by: Sabih Gerez, University of wente, March, 4 5 Selection/adaptation by: Sabih Gerez, University of wente, March, 4 Functional languages : a textual representation of an SFG Example of a functional description 5. If then else constructs are possible Semantics = multiplexer z = if ( c ) => a if ( ) => b else d c no overlap the conditions always an else clause a b d z f = e c h = f - g g = c d e = a b a b c d - - c c c4 Implementation freedom (assumg 4 cycles are available) Selection/adaptation by: Sabih Gerez, University of wente, March, 4 7 Selection/adaptation by: Sabih Gerez, University of wente, March, 4 8

3 Discussion: functional descriptions Advantages functional languages no implementation bias maximum parallelism, maximum freedom Disadvantages requires powerful mappg tools to exploit the freedom sometimes diicult to write e.g. update one element of an array requires a copy of the whole array (i :.. ) y[i] = if (i==7) then x[i] else - Procedural descriptions basic element = a variable assignment operator stores variables registers multiple assignment is possible semantics are defed by statement order ; expresses sequencg s = ; for i = to s = s a [ i ] ; ==> procedural languages Selection/adaptation by: Sabih Gerez, University of wente, March, 4 9 Selection/adaptation by: Sabih Gerez, University of wente, March, 4 Example of procedural descriptions Discussion: procedural descriptions a b c d - c c c4 e = a b; f = e c; g = c d; h = f - g; - c c c4 g = c d; e = a b; f = e c; h = f - g; - Disadvantages implementation bias limited parallelism unless powerful dataflow analysis Advantages steerg by the user rend towards C and C e.g. SystemC Synopsys, Frontier Design/Adelante/ARM, Coware,... Selection/adaptation by: Sabih Gerez, University of wente, March, 4 Selection/adaptation by: Sabih Gerez, University of wente, March, 4

4 Procedural descriptions Data-flow analysis more freedom: advantage or disadvantage? spec SFG implementation Direct implementation process : example variable x,y,z: t; x = i - i; y = i - i4; if (x > i5) then 4 z = x i; else 5 z = x - y; end if; o = z i7; 7 o = i8 i9; end process control flow dataflow CDFG = max // 7 Selection/adaptation by: Sabih Gerez, University of wente, March, 4 Selection/adaptation by: Sabih Gerez, University of wente, March, 4 4 process : gcd variable xx, yy : t wait until start ; ready <= ; xx = x; 4 yy = y; 5 while (xx yy) loop if (xx > yy) 7 then xx = xx - yy; 8 else yy = yy - xx; end if; 9 end while loop; res <= xx; ready <= ; end process control flow process : gcd variable xx, yy : t wait until start ; ready <= ; xx = x; 4 yy = y; 5 while (xx yy) loop if (xx > yy) 7 then xx = xx - yy; 8 else yy = yy - xx; end if; 9 end while loop; res <= xx; ready <= ; end process start ready 5 4 yy xx 7 8 data flow res Selection/adaptation by: Sabih Gerez, University of wente, March, 4 5 Selection/adaptation by: Sabih Gerez, University of wente, March, 4

5 ready yy xx res control flow data flow CDFG = max // Basics of Synchronous Design: opics Already covered: Description of algorithms: functional, procedural, flow graphs. Next topics: Implementation methods: one-to-one mappg function multiplexg time foldg Selection/adaptation by: Sabih Gerez, University of wente, March, 4 7 Selection/adaptation by: Sabih Gerez, University of wente, March, 4 8 Basic mappg techniques (no loops) Given a SFG (operations) library of module types (operators: adders, subtractors...) : correspondence operations - operators throughput Fd an implementation with mimal area. remark: dierent abstraction levels are possible: bit, word, function notation: operation operator addition adder multiplication multiplier algorithmic delay(z - ) ed flipflop Remark: puts and puts are also modelled this way Basic mappg techniques (no loops) timg constrat e.g. A produces an put signal with a specified rate cost function e.g. mimal area SFG library implementation A C B D : correspondence operations - operators: not essential but it simplifies the discussion Selection/adaptation by: Sabih Gerez, University of wente, March, 4 9 Selection/adaptation by: Sabih Gerez, University of wente, March, 4

6 Basic mappg techniques (no loops) one-to-one mappg one-to-one mappg function multiplexg time foldg a b c d put_a put_b put_c put_d t t - t multiplier_ subtractor t adder t t multiplier_ x put_x R = f f c s multiplex factor = ypically but exceptions are possible Selection/adaptation by: Sabih Gerez, University of wente, March, 4 R = f f c s > Allocation = how many operators for each type assignment = lk between operation and operator timg? Selection/adaptation by: Sabih Gerez, University of wente, March, 4 trivial one-to-one mappg: timg analysis logic logic logic logic Combatorial logic (implementation or samplg ) one-to-one mappg: timg analysis for fallg-edge sensitive flipflops (risg edge more common) setup hold setup hold logic skew cycle time = clk_to_q longest_logic_path setup _skew clk_to_q shortest_logic_path _skew > hold Selection/adaptation by: Sabih Gerez, University of wente, March, 4 Selection/adaptation by: Sabih Gerez, University of wente, March, 4 4

7 allocation assignment pipelg one-to-one mappg: pipelg ed flipflop Selection/adaptation by: Sabih Gerez, University of wente, March, 4 5 Analyze timg if OK then stop else pipelg one-to-one mappg critical path = cc = 4ns throughput = 5 MHz latency = cc = 4ns 4 5 Selection/adaptation by: Sabih Gerez, University of wente, March, 4 time (cc) critical path = cc = ns Applications (see later) throughput = MHz - prog. processors latency = 4cc = 4ns - loops = SW pipelg -design ASUs A B C - design D digital filters - SDRAMs time (cc) a b Selection/adaptation by: Sabih Gerez, University of wente, March, 4 7 y y = a [t-] b [t-] one-to-one mappg a b y [t] = y [t-] y [t-]= a [t-] b [t-] Retimg = shiftg flipflops that are already present the circuit Pipelg also allows an exchange of flipflops with the environment. As a consequence the IO timg behavior changes (time shape). he number of flipflops can change by retimg. y Mimal Iteration Period he mimal iteration period of a data-flow graph is given by: m = max all loops L total computation delay of L number of delay elements L Retimg does not change this lower bound (it does not change the delay element count). See also slides VLSI System Design: highlevel transformations. Selection/adaptation by: Sabih Gerez, University of wente, March, 4 8

8 one-to-one mappg: retimg applied twice one-to-one mappg Important property: retimg and pipelg can not change the number of flipflops a loop the circuit. Selection/adaptation by: Sabih Gerez, University of wente, March, 4 9 Selection/adaptation by: Sabih Gerez, University of wente, March, 4 ime(cc) = 4 m (a) = 5 ime(cc) ime(cc) = 4 m = m (b) = 4 (c) = Selection/adaptation by: Sabih Gerez, University of wente, March, 4

Let s put together a Manual Processor

Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce