Managing High-Speed Clocks

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1 Managing High-Speed s & Greg Steinke Director, Component Applications Managing High-Speed s Higher System Performance Requires Innovative ing Schemes What Are The Possibilities?

2 High-Speed ing Schemes Synchronous ing Source-Synchronous ing - Synchronization (CDS) - Recovery (CDR) High-Speed ing Schemes Synchronous ing Source-Synchronous ing - Synchronization (CDS) - Recovery (CDR) 2

3 Synchronous ing One Drives All Devices in System f MAX Limited by t CO, t PD &t SU Source Destination High-Speed ing Schemes Synchronous ing Source-Synchronous ing - Synchronization (CDS) - Recovery (CDR) 3

4 Source-Synchronous ing Signal Transmitted with Board Skew Reduces System Performance Source Destination Source-Synchronous Benefit Source-Synchronous ing Enables Transfer at High Speeds Performance No Longer Limited by t CO, t PD & t SU Maximum Performance Factors z Edge Rate of Driver z Skew between Signals & Signals 4

5 Source-Synchronous Drawbacks Every Chip-to-Chip Transfer Introduces New Domain Receiver Must Manage Multiple Domains Performance Affected by Board Skew Skew Reduction Complicates Board Design Source-Synchronous Timing Analysis Transmitter Skew, Board Skew & Jitter Reduce System Performance Transmitter Skew Board Skew Source Destination Jitter 5

6 Source-Synchronous Parameters Parameters Required for Timing Analysis Time-Unit Interval (TUI) z Bit Period: 2 ns for 500-Mbit Transfer Channel-to-Channel Skew (TCCS) z Skew between Transmitter Outputs Timing Parameters Sampling Window (SW) Time During Which Is Sampled at Receiver Receiver Skew Margin (RSKM) Remaining Margin to Accommodate Board Skew & PLL Jitter 6

7 Successful Transfer Receiver Samples on Falling Edge 05-MHz 840-MHz Internally Generated Channel 0 Channel Channel Must Be Valid During Sampling Window TCCS & Board Skew Change to Alignment Excessive TCCS Or Board Skew 05-MHz 840-MHz Internally Generated Channel 0 Channel Channel Excessive Skew Causes Invalid During Sampling Window TCCS & Board Skew Change to Alignment 7

8 Quantifying Timing Budget Example: 840-Mbps Transfer TUI = /840 Mbps = 90 ps TCCS = 400 ps SW = 440 ps RSKM = ½ (TUI - SW - TCCS) = 75 ps Time-Unit Interval (TUI) TCCS RSKM SW RSKM TCCS Sampling Edge High-Speed ing Schemes Synchronous ing Source-Synchronous ing - Synchronization (CDS) - Recovery (CDR) 8

9 CDS Expands Possibilities Entire System Can Operate Using Single Eases Printed Circuit Board (PCB) Layout Requirements Permits More Flexible ing Topologies Unlimited Skew Tolerance Internally Synchronizes to Tx Skew Channel Channel N Rx System Tx N CDS Options Single-Bit - Synchronization (CDS) Used for Point-to-Point Connections Compensates for Board Skew up to 50% of TUI Multi-Bit CDS Compensates for Any Board Skew Enables Multi-Point Applications 9

10 Single-Bit CDS Implementation CDS Circuitry Selects Appropriate Phase Independently at Each Channel Calibrated with Training Pattern Serial Input D D Synchronized System D RX Phase- Locked Loop (PLL) 0 Output 90 Output D Control Logic Selects Register with Expected Pattern Single-Bit CDS Implementation Selects of 5 Strobes Covering Bit Period Maintains Byte Alignment 05 MHz Channel º Internal -90º Internal 0º Internal Selected Phase 90º Internal 80º Internal 0

11 Multi-Bit CDS Compensates for Unlimited Board Skew RSKM Doesn t Limit Performance Uses Eight Strobes z Cover Two Bit Periods z Capture with Any Skew Byte Alignment Performed in Logic Elements Multi-Bit CDS Implementation APEX II Device Serial Dedicated Circuit CDS Bit Alignment Circuit Serial- Parallel Converter Byte Alignment Circuit System Logic

12 Multi-Bit CDS Alignment Implement Bit & Byte Alignment by Using Two Stages of Training Patterns CDS Circuit Recognizes First Training Pattern for Bit Alignment Logic Recognizes Second Training Pattern for Byte Alignment ([DPSOH'HVLJQ3URYLGHG IRU%\WH$OLJQPHQW System Using Multi-Bit CDS Received at Master Is Skewed by Transmitter t CO Variation & Board Skew Multi-Bit CDS Compensates for Skew Control Signal Initiates CDS Pattern $3(;,, N: Topology Control Signal Initiates Byte Alignment Pattern Control Circuitry & Pattern Detect Logic for Every RX Channel $3(;,, A Master $3(;,, C B $3(;,, 2

13 CDS Tradeoffs Benefits Calibrates Receiving Device for Transmitter or Board Skew Receiver Does Not Need to Manage Multiple Domains Drawbacks Transmitters Must Be ed from Same System Need Training Pattern Multi-Bit CDS Requires Byte Alignment Logic High-Speed ing Schemes Synchronous ing Source-Synchronous ing - Synchronization (CDS) - Recovery (CDR) 3

14 CDR Reference Is Used Trace Lengths Need Not Match Each Source & Destination May Have Individual Source Destination CDR Implementation Encoded into Stream PLL Recovers from Transitions.25 GBit 25 MHz Serialto-Parallel 0-Bit Bus FIFO Reference Recovery PLL.25GHz System Divider 25 MHz Recovered to System 4

15 CDR Benefits Receiver Recovers Individual s from Each Incoming Channel Each Channel Can Have Phase Variation Transmitters Can Operate on Multiple Crystals Each Channel Can Have Limited Frequency Variation CDR Drawbacks Encoding Schemes Used to Ensure Maximum Run Length Transitions Required for Recovery Some Channel Bandwidth Used to Encode the.25-gbit Bandwidth Used for.00-gbit Buffering Required to Accommodate Frequency Variation 5

16 ing Scheme Summary Benefits Synchronous Easy to Design Source- Synchronous CDS Higher Performance ƒ Board Skew Not an Issue ƒ Receiver Has One Domain CDR ƒ Board Skew Not an Issue ƒ Source Flexibility Disadvantages Lower Performance ƒ Must Control Board Skew ƒ Must Design with Multiple Domains ƒ Must Use Training Pattern ƒ Must Use Byte Alignment Circuit ƒ Must Encode ƒ Encoding Scheme Consumes Bandwidth Device Support All APEX 20KE, APEX 20KC, APEX II, Mercury APEX II Mercury 6

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