Packages. 8-Lead PDIP IR2184

Transcription

1 Data Sheet No. PD7 revg Features Floating channel designed for bootstrap operation Fully operational to +V Tolerant to negative transient voltage dv/dt immune Gate drive supply range from to V Undervoltage lockout for both channels.v and V input logic compatible Matched propagation delay for both channels Logic and power ground +/- V offset. Lower di/dt gate driver for better noise immunity Output source/sink current capability.a/.8a Also available LEAD-FREE (PbF) Description The IR8()(S) are high voltage, high speed power MOSFET and IGBT drivers with dependent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to.v logic. The output drivers feature a Typical Connection Packages IR8()(S) & (PbF) HALF-BRIDGE DRIVER 8-Lead PDIP IR8 8-Lead SOIC IR8S -Lead PDIP IR8 -Lead SOIC IR8S IR8/IR8/IR8 Feature Comparison high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to volts. IR8 IR8 (Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

2 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Units V B High side floating absolute voltage -. V S High side floating supply offset voltage V B - V B +. V HO High side floating output voltage V S -. V B +. V CC Low side and logic fixed supply voltage -. V LO Low side output voltage -. V CC +. DT Programmable dead-time pin voltage (IR8 only) V SS -. V CC +. V IN Logic input voltage (IN & SD) V SS -. V SS + V SS Logic ground (IR8 only) V CC - V CC +. dv S /dt Allowable offset supply voltage transient V/ns P D Package power T A + C (8-lead PDIP). (8-lead SOIC). (-lead PDIP). W (-lead SOIC). Rth JA Thermal resistance, junction to ambient (8-lead PDIP) (8-lead SOIC) (-lead PDIP) 7 C/W (-lead SOIC) T J Junction temperature T S Storage temperature - C T L Lead temperature (soldering, seconds) Recommended Operating Conditions The input/output logic timing diagram is shown in figure. For proper operation the device should be used within the recommended conditions. The V S and V SS offset rating are tested with all supplies biased at V differential. Symbol Definition Units VB High side floating supply absolute voltage V S + V S + V S High side floating supply offset voltage Note V HO High side floating output voltage V S V B V CC Low side and logic fixed supply voltage V LO Low side output voltage V CC V V IN Logic input voltage (IN & SD) V SS V SS + DT Programmable dead-time pin voltage (IR8 only) V SS V CC V SS Logic ground (IR8 only) - T A Ambient temperature - C Note : Logic operational for V S of - to +V. Logic state held for V S of -V to -V BS. (Please refer to the Design Tip DT97- for more details). Note : IN and SD are internally clamped with a.v zener diode. V

3 Dynamic Electrical Characteristics V BIAS (V CC, V BS ) = V, V SS = COM, C L = pf, T A = C, DT = VSS unless otherwise specified. Symbol Definition Units Test Conditions ton Turn-on propagation delay 8 9 V S = V toff Turn-off propagation delay 7 V S = V or V tsd Shut-down propagation delay 8 7 MTon Delay matching, HS & LS turn-on 9 MToff Delay matching, HS & LS turn-off tr Turn-on rise time V S = V tf Turn-off fall time V S = V DT Deadtime: LO turn-off to HO turn-on(dtlo-ho) & 8 RDT= HO turn-off to LO turn-on (DTHO-LO) µsec RDT = k MDT Deadtime matching = DTLO - HO - DTHO-LO nsec RDT= RDT = k Static Electrical Characteristics V BIAS (V CC, V BS ) = V, V SS = COM, DT= V SS and T A = C unless otherwise specified. The V IL, V IH and I IN parameters are referenced to V SS /COM and are applicable to the respective input leads: IN and SD. The V O, I O and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol Definition Units Test Conditions V IH Logic input voltage for HO & logic for LO.7 V CC = V to V V IL Logic input voltage for HO & logic for LO.8 V CC = V to V V SD,TH+ SD input positive going threshold.7 V CC = V to V V SD,TH- SD input negative going threshold.8 V V CC = V to V V OH High level output voltage, V BIAS - V O. I O = A V OL Low level output voltage, V O. I O = A I LK Offset supply leakage current V B = V S = V µa I QBS Quiescent V BS supply current V IN = V or V I QCC Quiescent V CC supply current... ma V IN = V or V I IN+ Logic input bias current IN = V, SD = V µa I IN- Logic input bias current. IN = V, SD = V V CCUV+ V CC and V BS supply undervoltage positive going V BSUV+ threshold V CCUV- V CC and V BS supply undervoltage negative going V BSUV- threshold V CCUVH Hysteresis..7 V V BSUVH I O+ Output high short circuit pulsed current..9 V O = V, PW µs I O- Output low short circuit pulsed current.8. A V O = V, PW µs nsec

4 Functional Block Diagrams 8 SD UV DETECT DELAY IN VS HO VB PULSE FILTER HV LEVEL SHIFTER R R S Q UV DETECT PULSE GENERATOR VSS/COM LEVEL SHIFT VSS/COM LEVEL SHIFT +V DEADTIME COM LO VCC 8 SD UV DETECT DELAY IN DT VSS VS HO VB PULSE FILTER HV LEVEL SHIFTER R R S Q UV DETECT PULSE GENERATOR VSS/COM LEVEL SHIFT VSS/COM LEVEL SHIFT +V DEADTIME COM LO VCC

5 Lead Definitions Symbol Description IN Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM for IR8 and VSS for IR8) SD DT VSS V B HO V S V CC LO COM Logic input for shutdown (referenced to COM for IR8 and VSS for IR8) Programmable dead-time lead, referenced to VSS. (IR8 only) Logic Ground (8 only) High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return Lead Assignments IN V B 8 IN V B 8 SD HO 7 SD HO 7 COM V S COM V S LO V CC LO V CC 8-Lead PDIP 8-Lead SOIC IR8 IR8S IN IN SD V B SD V B VSS HO VSS HO DT V S DT V S COM COM LO 9 LO 9 7 V CC 8 7 V CC 8 -Lead PDIP -Lead SOIC IR8 IR8S

6 Figure. Input/Output Timing Diagram Figure. Switching Time Waveform Definitions Figure. Shutdown Waveform Definitions Figure. Deadtime Waveform Definitions Figure. Delay Matching Waveform Definitions

7 Turn-on Propagation Delay (ns) Turn-on Propagation Delay (ns) 8 8 Figure A. Turn-on Propagation Delay FigureB. Turn-on Propagation Delay vs. Supply Voltage 7 7 Turn-off Propagation Delay (ns) Turn-off Propagation Delay (ns) 8 Figure A. Turn-off Propagation Delay Figure B. Turn-off Propagation Delay vs. Supply Voltage 7

8 SD Propagation Delay (ns) SD Propagation Delay (ns) Figure A. SD Propagation Delay Figure B. SD Propagation Delay vs. Supply Voltage Turn-on Rise Time (ns) 8 Turn-on Rise Time (ns) Figure 7A. Turn-on Rise Time 8 Figure 7B. Turn-on Rise Time vs. Supply Voltage 8

9 8 8 Turn-off Fall Time (ns) Typ Turn-off Fall Time (ns) Figure 8A. Turn-off Fall Time 8 Figure 8B. Turn-off Fall Time vs. Supply Voltage 9 9 Deadtime (ns) 7 Deaduime (ns) Figure 9A. Deadtime 8 Supply Voltage (v) Figure 9B. Deadtime vs. Supply Voltage 9

10 7 Deadtime ( Ηs) R DT (KΗ) Logic "" Input Voltage (V) Figure 9C. Deadtime vs. R DT Figure A. Logic "" Input Voltage Logic "" Input Voltage (V) 8 Logic "" Input Voltage (V) Figure B. Logic "" Input Voltage vs. Supply Voltage Figure A. Logic "" Input Voltage

11 Logic "" Input Voltage (V) 8 Figure B. Logic "" Input Voltage vs. Supply Voltage SD Input Positive Going Threshold (V) Figure A. SD Input Positive Going Threshold SD Input Positive Going Threshold (V) 8 Figure B. SD Input Positive Going Threshold vs. Supply Voltage SD Input Negative Going Threshold (V) Figure A. SD Input Negative Going Threshold

12 SD Input Negative Going Threshold (V) 8 High Level Output (V) Figure B. SD Input Negative Going Threshold vs. Supply Voltage Figure A. High Level Output. High Level Output (V) Low Level Output (V) Figure B. High Level Output vs. Supply Voltage Figure A. Low Level Output

13 Low Level Output (V) Offset Supply Leakage Current ( ΗA) Figure B. Low Level Output vs. Supply Voltage Figure A. Offset Supply Leakage Current vs. Temperature Offset Supply Leakage Current ( ΗA) V BS Supply Current ( ΗA) V B Boost Voltage (V) Figure B. Offset Supply Leakage Current vs. V B Boost Voltage Figure 7A. V BS Supply Current

14 V BS Supply Current ( ΗA) V CC Supply Current (ma) V BS Floating Figure 7B. V BS Supply Current vs. V BS Floating Supply Voltage Figure 8A. V CC Supply Current V CC Supply Current (ma) 8 Logic "" Input Bias Current ( ΗA) V CC Figure 8B. V CC Supply Current vs. V CC Supply Voltage Figure 9A. Logic "" Input Bias Current

15 Logic "" Input Bias Current ( ΗA) 8 8 Figure 9B. Logic "" Input Bias Current vs. Supply Voltage Logic "" Input Bias Current ( ΗA) Figure A. Logic "" Input Bias Current Logic "" Input Bias Current ( ΗA) 8 Figure B. Logic "" Input Bias Current vs. Supply Voltage V CC and V BS UV Threshold (+) (V) Figure. V CC and V BS Undervoltage Threshold (+)

16 V CC and V BS UVThreshold (-) (V) Figure. V CC and V BS Undervoltage Threshold (-) Output Source Current (A) Figure A. Output Source Current. Output Source Current (A) 8 Output Sink Current (A) Figure B. Output Source Current vs. Supply Voltage Figure A. Output Sink Current

17 Output Sink Current (A) Temprature ( o C) 8 v 7v v 8 Figure B. Output Sink Current vs. Supply Voltage Figure.IR8 vs.frequency (IRFBC ), =Ω,V CC =V 8 v 7v v 8 v 7v v Figure.IR8 vs.frequency (IRFBC), =Ω,V CC =V Figure.IR8 vs.frequency (IRFBC), =Ω,V CC =V 7

18 v 7v v 8 8 v 7v v Figure.IR8 vs.frequency (IRFPE), =Ω,V CC =V Figure.IR8 vs.frequency (IRFBC), =Ω,V CC =V 8 v 7v v 8 v 7v v Figure.IR8 vs.frequency (IRFBC), =Ω,V CC =V Figure 7.IR8 vs.frequency (IRFBC ), =Ω,V CC =V 8

19 v 7v 8 v 8 v 7v v Figure 8.IR8 vs.frequency (IRFPE), =Ω,V CC =V Figure 9.IR8s vs.frequency (IRFBC ), =Ω,V CC =V v 7v 8 Figure.IR8s vs.frequency (IRFBC), =Ω,V CC =V v 7v v 8 Figure.IR8s vs.frequency (IRFBC), =Ω,V CC =V v 9

20 V 7V V Tempreture ( o C) 8 8 v 7v v Figure. IR8s vs. Frequency (IRFPE), =Ω, V CC =V Figure. IR8s vs. Frequency (IRFBC), =Ω, V CC =V 8 v 7v v 8 v 7v v Figure. IR8s vs. Frequency (IRFBC), =Ω, V CC =V Figure. IR8s vs. Frequency (IRFBC), =Ω, V CC =V

21 8 v 7v v Figure. IR8s vs. Frequency (IRFPE), =Ω, V CC =V

22 8-Lead PDIP - - (MS-AB) A E X D 8 7 e B H. [.] A. [.] X.7 [.] FOOTPRINT 8X.7 [.8] 8X.78 [.7] DIM INC HES MILLIMETERS MIN MAX MIN MAX A A b.... c D E e. BASIC.7 BASIC e. BASIC. BASIC H K L y e A C y K x 8X b A. [.] C A B. [.] 8X L 7 8X c NOTES:. DIMENSIONING & TOLERANCING PER ASME Y.M-99.. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].. OUTLINE CONFORMS TO JEDEC OUTLINE MS-AA. 8-Lead SOIC DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE (MS-AA)

23 -Lead PDIP - - (MS-AC) -Lead SOIC (narrow body) -9 - (MS-AB)

24 LEADFREE PART MARKING INFORMATION Part number IRxxxxxx Date code YWW? IR logo Pin Identifier? MARKING CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - digit SPN code) Assembly site code Per SCOP - ORDER INFORMATION Basic Part (Non-Lead Free) 8-Lead PDIP IR8 order IR8 8-Lead SOIC IR8S order IR8S -Lead PDIP IR8 order IR8 -Lead SOIC IR8 order IR8S Leadfree Part 8-Lead PDIP IR8 order IR8PbF 8-Lead SOIC IR8S order IR8SPbF -Lead PDIP IR8 order IR8PbF -Lead SOIC IR8 order IR8SPbF Thisproduct has been designed and qualified for the industrial market. Qualification Standards can be found on IR s Web Site Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: Kansas St., El Segundo, California 9 Tel: () -7 //