IRS2092 PROTECTED DIGITAL AUDIO AMPLIFIER. Product Summary

Transcription

1 PROTECTED DIGITAL AUDIO AMPLIFIER Features Integrated analog input Class D audio amplifier driver in a small 16 pin package Floating inputs enable easy half bridge implementation Programmable bidirectional over-current protection with self-reset function Programmable preset deadtime for improved THD performances Start and stop click noise reduction High noise immunity 100 ratings deliver up to 500 W in output power Operates up to 800 khz RoHS compliant Typical Applications Home theater systems Mini component stereo systems Powered speaker systems General purpose audio power amplifiers Product Summary OFFSET (max) Gate driver Selectable Deadtime Io+ Io- OC protection delay (max) DC offset PWM frequency Error amplifier open loop gain A 1.2 A 25/40/65/105 ns 500 ns <20 m ~800 khz >60 db THD+N* (1kHz, 50W, 4Ω) 0.01 % Residual Noise* (AES-17 Filter) * Measured with recommended circuit Package Options 200 µrms Typical Connection Diagram SOIC16N PDIP16 1 IRS2092 AA CSH 16 +B INPUT 2 GND B 15 3 IN CSD S CC Speaker 6 SS LO 11 7 REF COM 10 cc 8 OCSET DT B International Rectifier October 24, 2013

2 Table of Contents Page Description 3 Simplified Block Diagram 4 Typical Application Diagram 4 Qualification Information 5 Absolute Maximum Ratings 6 Recommended Operating Conditions 7 Electrical Characteristics 8 Waveform Definitions 11 Functional Block Diagram 12 Input/Output Pin Equivalent Circuit Diagram 13 Lead Definitions 14 Lead Assignments 14 Package Details 15 Tape and Reel Details 16 Part Marking Information 17 Ordering Information International Rectifier October 24, 2013

3 Description The IRS2092 is a high voltage, high performance Class D audio amplifier driver with PWM modulator and protection. In conjunction with two external MOSFET and a few external components, a complete Class D audio amplifier with protection can be realized. International Rectifier s proprietary noise isolation technology allows high current gate drive stage and high speed low noise error amplifier reside on a single small silicon die. Open elements of PWM modulator section allow flexible PWM topology implementation International Rectifier October 24, 2013

4 Simplified Block Diagram FLOATING INPUT CSH AA B IN- OTA AA+SS 2 HIGH SIDE CS GND H LEEL H LEEL FLOATING HIGH SIDE H LEEL S CC SS CSD DEAD TIME LO PROTECTION CONTROL H LEEL H LEEL SD DT LOW SIDE CS COM REF OCSET DT Typical Application Diagram 47 kω 2.7 kω +B in 10 µf µf 3.3 kω 1 nf 3 10 µf nf 1 nf 5 10 µf kω kω 1.2 kω AA GND IN- CSH B S CSD CC SS LO REF COM OCSET DT IRS BA19WS 33 kω 10 kω IRF6645 MURS kω 10 Ω 22 µf 4.7 Ω IRF µf 10 Ω 3.3 kω cc kω 1 kω 150 pf 22 µh 0.1 µf 0.47 µf 1 Ω 0.1 µf Ω out -B International Rectifier October 24, 2013

5 Qualification Information Qualification Level Moisture Sensitivity Level Machine Model Human Body Model Charged Device Model IC Latch-Up Test RoHS Compliant Industrial (per JEDEC J 47E) Comments: This IC has passed JEDEC s Industrial qualification. IR s Consumer qualification level is granted by extension of the higher Industrial level. MSL2 SOIC16N (per IPC/JEDEC J-STD-020C) DIP16 Not applicable Class B (per JEDEC standard J22-A114D) Class 2 (per EIA/JEDEC standard EIA/J22-A115-A) Class I (per JEDEC standard J22-C101C) Class I, Level A (per J78A) Yes Qualification standards can be found at International Rectifier s web site Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information International Rectifier October 24, 2013

6 Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM; all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions Symbol Definition Min Max Units B High side floating supply voltage S High side floating supply voltage B -20 B +0.3 High side floating output voltage S -0.3 B +0.3 CSH CSH pin input voltage S -0.3 B +0.3 CC Low side fixed supply voltage LO Low side output voltage -0.3 cc+0.3 AA Floating input positive supply voltage (See I AAZ ) 210 SS Floating input negative supply voltage -1 (See I SSZ ) GND +0.3 GND Floating input supply ground voltage SS -0.3 (See I SSZ ) AA +0.3 (See I AAZ ) I IN- Inverting input current --- ±3 ma CSD SD pin input voltage SS -0.3 AA +0.3 pin input voltage SS -0.3 AA +0.3 DT DT pin input voltage -0.3 CC +0.3 OCSET OCSET pin input voltage -0.3 CC +0.3 I AAZ Floating input positive supply zener clamp current I SSZ Floating input negative supply zener clamp current I CCZ Low side supply zener clamp current ma I BSZ Floating supply zener clamp current I OREF Reference output current d S /dt Allowable s voltage slew rate /ns d SS /dt Allowable ss voltage slew rate /ms Pd Maximum power T A +25C SOIC16N DIP W Rth JA Thermal resistance, Junction to ambient SOIC16N DIP C/W T J Junction Temperature C T S Storage Temperature C T L Lead temperature (soldering, 10 seconds) C IN- contains clamping diode to GND. DD IN+, GND - SS, CC -COM and B - S contain internal shunt zener diodes. Please note that the voltage ratings of these can be limited by the clamping current. For the rising and falling edges of step signal of 10. SS =15 to International Rectifier October 24, 2013

7 Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions below. The s and COM offset ratings are tested with supplies biased at AA - SS =10, CC =12 and B - S =12. All voltage parameters are absolute voltages referenced to COM; all currents are defined positive into any lead. Symbol Definition Min. Max. Units B High side floating supply absolute voltage S +10 S +18 S High side floating supply offset voltage 200 I AAZ Floating input positive supply zener clamp current 1 11 I SSZ Floating input negative supply zener clamp current 1 11 ma SS Floating input supply absolute voltage High side floating output voltage s B CC Low side fixed supply voltage LO Low side output voltage 0 CC GND GND pin input voltage SS AA IN- Inverting input voltage GND -0.5 GND +0.5 CSD CSD pin input voltage SS AA pin input voltage SS AA C pin phase compensation capacitor to GND 1 - nf DT DT pin input voltage 0 CC I OREF Reference output current to COM ma OCSET OCSET pin input voltage CSH CSH pin input voltage s B dss/dt Allowable ss voltage slew rate upon power-up - 50 /ms I PW Input pulse width 10 - ns f SW Switching Frequency khz T A Ambient Temperature C Logic operational for s equal to 5 to Logic state held for s equal to 5 to BS. Nominal voltage for REF is 5.1. I OREF of ma dictates total external resistor value on REF to be 6.3 kω to 16.7 kω. GND input voltage is limited by I AAZ and I SSZ. SS ramps up from 0 to 200. Output logic status may not respond correctly if input pulse width is smaller than the minimum pulse width International Rectifier October 24, 2013

8 Electrical Characteristics CC, BS = 12, SS = S =COM=0, AA =10, C L =1 nf and T A =25 C unless otherwise specified. Symbol Definition Min Typ Max Units Test Conditions Low Side Supply U CC+ cc supply ULO positive threshold U CC- cc supply ULO negative threshold U CCHYS U CC hysteresis I QCC Low side quiescent current ma DT = CC CLAMPL Low side zener diode clamp voltage I CC =5 ma High Side Floating Supply U BS+ High side well ULO positive threshold U BS- High side well ULO negative threshold U BSHYS U BS hysteresis I QBS High side quiescent current ma I LKH High to Low side leakage current µa B = S =200 CLAMPH High side zener diode clamp voltage I BS =5 ma Floating Input Supply U AA+ A+, A- floating supply ULO SS =0, GND pin positive threshold from SS floating U AA- A+, A- floating supply ULO SS =0, GND pin negative threshold from SS floating U AAHYS U AA hysteresis SS =0, GND pin floating I QAA0 Floating Input positive quiescent AA =10, SS =0, supply current CSD =SS I QAA1 Floating Input positive quiescent ma AA =10, SS =0, supply current CSD =AA I QAA2 Floating Input positive quiescent AA =10, SS =0, supply current CSD =GND I LKM Floating input side to Low side µa AA = SS = GND = leakage current 100 CLAMPM+ AA floating supply zener diode clamp voltage, positive, with respect to GND I AA =5 ma, I SS =5 ma, GND =0, CSD =SS CLAMPM- SS floating supply zener diode clamp voltage, negative, with respect to GND I AA =5 ma, I SS =5 ma, GND =0, CSD =SS International Rectifier October 24, 2013

9 Electrical Characteristics (cont d) CC, BS = 12, SS = S =COM=0, AA =10, C L =1 nf and T A =25 C unless otherwise specified. Audio Input ( GND =0, AA =5, SS =-5) OS Input offset voltage m I BIN Input bias current na BW Small signal bandwidth MHz C =2 nf, Rf=3.3 kω OTA Output voltage AA-1 - SS+1 g m OTA transconductance ms IN- =10 m G OTA gain db Nrms OTA input noise voltage mrms BW=20 khz, Resolution BW=22 Hz Fig.5 SR Slew rate - ±5 - /us C =1 nf CMRR Common-mode rejection ratio db PSRR Supply voltage rejection ratio PWM comparator PWM comparator threshold in ( th PWM - AA - - SS )/2 pin star-up local oscillation f OTA MHz frequency CSD =GND Protection REF Reference output voltage I OREF =0.5 ma th OCL Low side OC threshold in s OCSET=1.2, Fig.6 th OCH High side OC threshold in CSH 1.1+ s 1.2+ s 1.3+ s s=200, th1 CSD pin shutdown release threshold 0.62x AA 0.70x AA 0.78x AA th2 CSD pin self reset threshold 0.26x AA 0.30x AA 0.34x AA I CSD+ CSD pin discharge current µa CSD = SS +5 I CSD- CSD pin charge current CSD = SS +5 t SD Shutdown propagation delay from CSD > SS + th OCH to Shutdown t OCH Propagation delay time from CSH > th OCH to Shutdown ns Fig.3 t OCL Propagation delay time from s> th OCL to Shutdown Fig International Rectifier October 24, 2013

10 Electrical Characteristics (cont d) CC, BS = 12, SS = S =COM=0, AA =10, C L =1 nf and T A =25 C unless otherwise specified. Gate Driver Io+ Output high short circuit current (Source) A o=0, PW<10 µs Io- Output low short circuit current (Sink) A o=12, PW<10 µs OL Low level out put voltage LO COM, - S OH High level out put voltage CC LO, B Io=0 A ton High and low side turn-on propagation delay DT = CC toff High and low side turn-off propagation delay DT = CC tr Turn-on rise time tf Turn-off fall time Deadtime: LO turn-off to turnon (DT LO- ) & turn-off to LO DT1 DT > DT1, turn-on (DT -LO ) ns Deadtime: LO turn-off to turnon (DT LO- ) & turn-off to LO DT1 > DT > DT2, DT2 turn-on (DT -LO ) Deadtime: LO turn-off to turnon (DT LO- ) & turn-off to LO DT3 DT2 > DT > DT3, turn-on (DT -LO ) Deadtime: LO turn-off to turnon (DT LO- ) & turn-off to LO DT4 DT3 > DT > DT4, turn-on (DT -LO ) DT = DT4 DT1 DT mode select threshold xcc 0.57xcc 0.63xcc DT2 DT mode select threshold xcc 0.36xcc 0.40xcc DT3 DT mode select threshold xcc 0.23xcc 0.25xcc International Rectifier October 24, 2013

11 Waveform Definitions 50% 50% th1 ton(l) toff(l) CSD toff(h) 90% ton(h) LO 10% 90% DTLO- DT-LO 90% /LO 10% tsd Figure 1: Switching Time Waveform Definitions Figure 2: CSD to Shutdown Waveform Definitions CSH thoch S S thocl 90% 90% LO tocl toch Figure 3: S > th OCL to Shutdown Waveform Figure 4: CSH > th OCH to Shutdown Waveform 820 Ω 1 IRS2092 AA CSH µf 10 µf 820 Ω 3.3 µf 100 Ω 47 kω 2nF 2 nf GND IN- CSD SS B S CC LO REF COM Ω 8 OCSET DT 9 10 Ω 10 µf 10 µf 10 Ω 100 kω ` LT µf 100 Ω 10 kω 100 Ω NOISE OUT GND 10 nf Figure 5: OTA input noise voltage mesurent circuit International Rectifier October 24, 2013

12 Functional Block Diagram: IRS2092 AA CLICK NOISE ELLIMINATION FLOATING INPUT U DETECT CSH B IN- GND SS 6 6 ` OTA ENABLE U DETECT ` AA+SS 2 PWM MODULATOR H LEEL H LEEL HIGH SIDE CS FLOATING HIGH SIDE 5 REG U U DETECT Q H LEEL 20.4 S CC DEAD TIME CSD LO CHARGE/ DISCHARGE PROTECTION CONTROL H LEEL H LEEL SD DT 20.4 LOW SIDE CS COM REF OCSET DT International Rectifier October 24, 2013

13 Input/Output Pin Equivalent Circuit Diagrams: IRS2092 B AA IN- 6 Zener 20 Clamp S GND SS 6 Zener Clamp CC CC LO COM AA CC or CSD DT, REF or OCSET SS COM International Rectifier October 24, 2013

14 IRS2092 Lead Definitions: IRS2092 Pin # Symbol Description 1 AA Floating input positive supply 2 GND Floating input supply return 3 IN- Analog inverting input 4 Phase compensation input, comparator input 5 CSD Shutdown timing capacitor 6 SS Floating input negative supply 7 REF 5 reference voltage to program OCSET pin 8 OCSET Low side over current threshold setting 9 DT Deadtime program input 10 COM Low side supply return 11 LO Low side output 12 CC Low side supply 13 S High side floating supply return 14 High side output 15 B High side floating supply 16 CSH High side over current sensing input Lead Assignments AA 1 16 CSH GND 2 15 B IN S CSD 5 12 CC SS 6 11 LO REF 7 10 COM OCSET 8 9 DT PDIP16 and SOIC16N International Rectifier October 24, 2013

15 Package Details: PDIP16 Package Details: SOIC16N International Rectifier October 24, 2013

16 Tape and Reel Details: SOIC16N LOADED TAPE FEED DIRECTION B A H D F C NOTE : CONTROLLING DIMENSION IN MM E G CARRIER TAPE DIMENSION FOR 16SOICN Metric Imperial Code Min Max Min Max A B C D E F G 1.50 n/a n/a H F D E C B A G H REEL DIMENSIONS FOR 16SOICN Metric Imperial Code Min Max Min Max A B C D E F n/a n/a G H International Rectifier October 24, 2013

17 Part Marking Information Part number IRS2092(S) Date code YWW? IR logo Pin 1 Identifier? P MARKING CODE Lead Free Released Non-Lead Free Released? XXXX Lot Code (Prod mode 4 digit SPN code) Assembly site code Per SCOP Ordering Information Base Part Number Standard Pack Package Type Complete Part Number Form Quantity PDIP16 Tube/Bulk 25 IRS2092PBF IRS2092 SOIC16N Tube/Bulk 45 IRS2092SPBF Tape and Reel 2500 IRS2092STRPBF The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied. For technical support, please contact IR s Technical Assistance Center WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California Tel: (310) International Rectifier October 24, 2013