Defect Engineering in Semiconductors

Transcription

1 Defect Engineering in Semiconductors Silicon Technology: problems of ultra large-scale l integration i Gettering in silicon Defect engineering in HgCdTe Near-surface defects in GaAs after diamond saw-cutting of wafers The EL2-defect in GaAs 1

2 Defect Engineering in Semiconductors Silicon is most important semiconductor degree of integration doubles after 2 years Si not best suited for all tasks (e.g. ultra-fast applications) but defect engineering is best known for this material MOS structures in 45 nm in current CPUs Gate oxide: about 5 nm = 10 atoms! Gate-Metall n-si n-si Cross section through 0.2 µm MOSFET 2

3 Moore s Law source: Wikipedia 3

4 Crystal growth, wafer cutting, polishing Oxid-Schicht Example: FET-technology photolithography 1: gate deposition n-conducting region by ion implantation photolithography 2: drain/source-isolation by ion implantation photolithography 3: deposition of Ohmic contacts several isolation layers and conducting wires isolation of chip s mounting in chip carriers and contacts packaging SAINT-technology (self-aligned implantation technology) 4

5 Increasing integration chips have larger area (1-2 cm 2 ); smaller structure (up to devices on a chip) critical: metallic impurities (Verunreinigungen), e.g. Fe, Ni and Cu <10 12 atoms/cm 3 already problematic (every atoms in Si!!) they may form precipitates (Ausscheidungen); are nuclei for larger defects may act as electrically active deep defects (Cu in Si is donor, in GaAs acceptor) very important for Cu technology, Cu is used as conductor in Si chips (better electrical and heat conductivity see below) Cu must be completely embedded (e.g. by TiN important demands: high thermal stability, small distortions, excellent etch-stop-properties, high resistance) irradiation defects become more important: α-radiator in packaging material as natural isotope may shorten lifetime of component drastically 5

6 Increasing integration: The RC limit with shrinking dimensions, speed of CPUs increase transistor size: -1 µm 66 MHz - 45 nm 4 GHz however: fundamental limit is signal propagation due to τ=rc limit resistivity of interconnects R becomes smaller when using Cu technology instead of Al (factor 1.6) isolation is up to now SiO 2 with high dielectric constant ε r = 4 source: materialstoday 1/2004,

7 Increasing integration: The RC limit no better conducting material instead of Cu is available (Au too expensive) thus, to decrease RC one must decrease the capacity between the wires this can only be done by decreasing ε r another material must be used for the isolation layers source: materialstoday 1/2004,

8 possible solution: nano-porous dielectrics (low-k material) nano-porous material can be used in the future however: mechanical problems, etc. source: materialstoday 1/2004,

9 Etching / polishing of Si-Wafers Si is rather hard and chemically very active; natural 2 nm SiO 2 -layer three-stage chemo-mechanical process (patent of 1963): 1. silica-grinding (schleifen) paste in a colloid (50 C, 20 µm at a removal of 1 µ/min) absolute scratch-free smooth surface, then 2. machine: 2. first step is repeated (ph-neutral, soft grinding paste) removal of only 1-2 µm Si 3. in same machine: without mechanical pressure (only chemical action) extremely clean agents required for < 10 9 impurities/cm 3 physical cleaning of surface in UHV by heating of sample also possible (not for wafer technology, but in research) Si still contains too high density of impurities -> gettering (gettern) of diffusing impurities necessary 9

10 Defect engineering in Si: Gettering of impurities Extrinsic gettering = impede of impurity penetration during annealing steps from backside of wafer by mechanical damage of rear wafer surface (Rückseite des Wafers) water of 70 bar together with 1 µm silica particles creation of stacking faults (Stapelfehler), dislocation rings, distorted regions with small depth (effective gettering centers: cm -2 ) performed before polishing of the front side for MOS-structures annealing at 1100 C sufficient; bipolar transistors require 1200 C (T m=1410 C) diffusion rather fast at this T getter efficiency drops during annealing thus required defect density and depth is different: MOS: µm bipolar: 2-4 µm also different damage applied, e.g. ion implantation REM-Aufnahme 10

11 Extrinsic Gettering in Si defects also by grinding (schleifen): procedure suitable for bipolar and MOS-structures enhanced gettering : additional layer is deposited at the rear surface of wafer (at C) without further mechanical treatment is rather expensive, but shows best gettering effect smaller higher h defect density 11

12 Intrinsic gettering in Si Oxygen precipitates (Ausscheidungen) in substrate: efficient getter centers only possible in Cz-Si (Czochalski grown); oxygen density is about cm -3 excess oxygen must be collected in precipitates before device is made however dissolve again, e.g. during annealing of implantation defects requirement: oxygen diluted zone at surface (no precipitates; there devices are made), but O- precipitates in the interior of the wafer: capture diffusing impurities solution: so-called HI-LO process (two-stage annealing) first: some hours at 1150 C O in vicinity of surface diffuses to SiO 2 cap layer; in interior: O remains e.g. [O]= cm -3 drops to cm -3 second step at 650 C: creation of nuclei for later precipitates whether O-depletion layer is formed depend on O concentration problem for this process: doesn t work well when oxide layer is very thin 2-step-process: 1150 C/16 h and 650 C/64 h 12

13 Intrinsic gettering in Si better getter-effect with 3-stage-process precipitates may be better controlled 1 step: dissolution of all precipitates (solubility at 1200 C: cm -3 ) and O- depletion zone forms at surface 2. step: 5-30h at 750 C nuclei for precipitates are formed (but not in nearsurface zone) time at 750 C determines number of nuclei, which are active at 1000 C 3. step: some hours at 1000 C formation of the final precipitates, which are not any more dissolved during subsequent process steps 13

14 3-step-formation of oxygen precipitates in Cz-Si Stage (1): 10h at 1050 C cross-section images (Querschnittsbild) of the complete wafer 14

15 Gettering by defects created during self-implantation of Si after high-energy (3.5 MeV) self-implantation of Si ( cm -2 ) and fast annealing (900 C, 30s): two new gettering zones appear at R p and R p /2 (R p = projected range of Si + ) visible by SIMS (Secondary Ion Mass Spectroscopy) profiling after intentional Cu contamination implantation Cu concent tration (cm -3 ) TEM image by P. Werner, MPI Halle SIMS R p /2 R p Depth (μm) at R p : gettering by interstitial-type dislocation loops (formed by excess interstitials during RTA) no defects visible by TEM at R p /2 What type are these defects? Interstitial type Vacancy type [3,4] [1,2] [1] R. A. Brown, et al., J. Appl. Phys. 84 (1998) 2459 [2] J. Xu, et al., Appl. Phys. Lett. 74 (1999) 997 [3] R. Kögler, et al., Appl. Phys. Lett. 75 (1999) 1279 [4] A. Peeva, et al., NIM B 161 (2000) 1090 Surface 15

16 Detection of gettering defects by positrons slow-positron beam technique is suitable tool to study open- volume defects in solids monoenergetic positrons are implanted to a certain depth positrons are trapped by defects and annihilate therein annihilation characteristics are changed -> Detection ti of openvolume defects possible 16

17 Gettering by defects created during self-implantation of Si surface R p /2 R p TEM Conclusions at 7.5 kev ref W/W r 1,15 1,10 1, ,00 0,95 Positron Annihilation 1, ,010 1, ,000 0,995 at 10 kev f S/S re R p /2: small vacancy clusters are gettering centers R p : dislocation loops are formed both defects are efficient gettering centers prospective way of defect engineering in Si technology (cm -3 ) Cu density SIMS R. Krause-Rehberg, et al. Appl. Phys. Lett. 77 (2000) Depth (μm) 17

18 Defect engineering in II-VI compounds: Hg Vacancies in Hg x Cd 1-x Te material for infrared detectors (has small band gap) Hg diffuses very easily, high vapor pressure of Hg at relatively low temperatures V Hg is acceptor and dominates electrical and optical behavior experimental finding: strong changes of [V Hg ] in THM-grown crystals R. Krause, et al., J. Cryst. Growth 101 (1990)

19 Control of V Hg concentration Concentration of Hg vacancies can be controlled by annealing under defined vapor pressure of Hg all technological steps must be performed under Hg vapor pressure 19

20 Defects in GaAs introduced by wafer cutting μm cutting of wafer with diamond-saw (by wire and blade saws) after cutting: surface destroyed, d defects several µm deep defect profile reaches far into the interior of the wafer study e.g. by positron annihilation careful etching and polishing necessary wafer roughness (Rauhigkeit) must be < 1 µm for a complete 6" wafer lk S/S bul sample 6 after sawing etching step 1 (2.5 μm) etching step 2 (2.5 μm) etching step 3 (2 μm) depth (μm) F. Börner et al. Appl. Surf. Sci. 149 (1999)

21 Cutting defects in GaAs: polishing Atomic force microscopy before/after polishing and etching heig ght (nm) heig ght (nm) 1,0 0,8 0,6 04 0,4 0, length (nm) 00 0, length (nm) 21

22 semi-insulating GaAs 15 years ago: high impurity level; Si was dominating n-conductivity in undoped material for many devices: substrate must be semi-insulating Cr dopant exhibit deep level in band gap when Cr-density is high enough, all Si-donors are compensated (but carrier mobility reduced) nowadays: impurity level is distinctly lower; carbon dominates, is acceptor EL2-defect ( electrically ll active defect No.2 ) is intrinsic i i antisite it defect (As Ga ) with deep levels at 770 mev (+/0) and 520 mev (2+/+) above valence band that means: the required semi-insulating properties appears automatically when the impurity density is lower then EL2 concentration ti after crystal growth: non-homogenous radial distribution over wafer annealing of the whole ingot at 800 C leads to homogenization 22

23 Compensation mechanism of semi-isolating GaAs self-compensation works only when [EL2] > [shallow acceptors] > [shallow donors] step 3 needs too high temperature, thus all carriers are compensated at normal temperatures condition can be fulfilled in pure semi-insulating GaAs by doping with C 23

24 one of mostly investigated defects The nature of the EL2 defect in GaAs exhibiting metastability at low T under light illumination stable metastable (Dabrowski 1988, Chadi 1988) there were several structural models of EL2 the above shown model was proven by positron annihilation i (Krause et al., 1990) 24