Fetch. Decode. Execute. Memory. PC update

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1 nwpc PC Nw PC valm Mmory Mm. control rad writ Data mmory data out rmmovl ra, D(rB) Excut Bch CC ALU A vale ALU Addr ALU B Data vala ALU fun. valb dste dstm srca srcb dste dstm srca srcb Ftch Dcod Excut icod:ifun M 1 [PC] ra:rb M 1 [PC+1] valc M 4 [PC+2] valp PC+6 vala [ra] valb [rb] vale valb + valc Dcod icod ifun ra rb valc valp A B M istr fil E Writ back Mmory Writ back PC updat M 4 [vale] vala PC valp Ftch Instruction mmory PC incrmnt PC

valb dste dstm srca srcb dste dstm srca srcb Ftch Dcod Excut icod:ifun M 1 [PC] ra:rb M 1 [PC+1] valc M 4

2 SEQ Opration #1 Combinational Loic CC ad ad Ports Data mmory Writ Writ Ports Stat PC ristr Cond. Cod ristr Data mmory istr fil All updatd as clock riss PC 0x00c istr fil Combinational Loic ALU Control Mmory rads Instruction mmory istr fil Data mmory

Cod ristr Data mmory istr fil All updatd as clock riss PC

3 SEQ Opration #2 Cycl 1: Cycl 2: Cycl 3: Cycl 4: Cycl 1 Cycl 2 Cycl 3 Cycl 4 0x000: irmovl $0x100,%bx # %bx <-- 0x100 0x006: irmovl $0x200,%dx # %dx <-- 0x200 0x00c: addl %dx,%bx # %bx <-- 0x300 CC < x00: j dst # Not takn Combinational Loic CC 100 PC 0x00c ad ad Ports Data mmory istr fil %bx = 0x100 Writ Writ Ports stat st accordin to scond irmovl instruction combinational startin to ract to stat chans

0x00: j dst # Not takn Combinational Loic CC 100 PC 0x00c ad ad Ports Data mmory istr fil %bx = 0x100

4 SEQ Opration #3 Cycl 1: Cycl 2: Cycl 3: Cycl 4: Cycl 1 Cycl 2 Cycl 3 Cycl 4 0x000: irmovl $0x100,%bx # %bx <-- 0x100 0x006: irmovl $0x200,%dx # %dx <-- 0x200 0x00c: addl %dx,%bx # %bx <-- 0x300 CC < x00: j dst # Not takn Combinational Loic CC PC 0x00c 0x00 ad ad Ports Data mmory istr fil %bx = 0x100 Writ Writ Ports 0x300 stat st accordin to scond irmovl instruction combinational nrats rsults for addl instruction

dst # Not takn Combinational Loic CC 100 000 PC 0x00c 0x00 ad ad Ports Data mmory istr fil %bx = 0x100 Writ

5 SEQ Opration #4 Cycl 1: Cycl 2: Cycl 3: Cycl 4: Cycl 1 Cycl 2 Cycl 3 Cycl 4 0x000: irmovl $0x100,%bx # %bx <-- 0x100 0x006: irmovl $0x200,%dx # %dx <-- 0x200 0x00c: addl %dx,%bx # %bx <-- 0x300 CC < x00: j dst # Not takn Combinational Loic CC 000 PC 0x00 ad ad Ports Data mmory istr fil %bx = 0x300 Writ Writ Ports stat st accordin to addl instruction combinational startin to ract to stat chans

000 0x00: j dst # Not takn Combinational Loic CC 000 PC 0x00 ad ad Ports Data mmory istr fil %bx =

6 SEQ Opration #5 Cycl 1: Cycl 2: Cycl 3: Cycl 4: Cycl 1 Cycl 2 Cycl 3 Cycl 4 0x000: irmovl $0x100,%bx # %bx <-- 0x100 0x006: irmovl $0x200,%dx # %dx <-- 0x200 0x00c: addl %dx,%bx # %bx <-- 0x300 CC < x00: j dst # Not takn Combinational Loic CC 000 PC 0x00 0x013 ad Writ Data mmory ad Writ Ports Ports istr fil %bx = 0x300 stat st accordin to addl instruction combinational nrats rsults for j instruction

0x00: j dst # Not takn Combinational Loic CC 000 PC 0x00 0x013 ad Writ Data mmory ad Writ Ports Ports

7 SEQ Summary Implmntation Exprss vry instruction as sris of simpl stps Follow sam nral flow for ach instruction typ Assmbl ristrs, mmoris, prdsind combinational blocks Connct with control Limitations

8 SEQ Summary Implmntation Exprss vry instruction as sris of simpl stps Follow sam nral flow for ach instruction typ Assmbl ristrs, mmoris, prdsind combinational blocks Connct with control Limitations Too slow to b practical In on cycl, must propaat throuh instruction mmory, ristr fil, ALU, and data mmory Would nd to run clock vry slowly Hardwar units only activ for fraction of clock cycl

$ALU, and data mmory Would nd to run clock vry slowly Hardwar units only activ for fraction of$

9 Piplin Ovrviw Gnral Principls of Piplinin Goal Difficultis Cratin a Piplind Y86 Procssor arranin SEQ Insrtin piplin ristrs Problms with data and control hazards

10 al-world Piplins: Car Washs Squntial Paralll Piplind Ida Divid procss into indpndnt stas Mov objcts throuh stas in squnc At any ivn tims, multipl objcts bin procssd

11 Computational Exampl 300 ps 20 ps Combinational Dlay = 320 ps Throuhput = 3.12 GOPS Systm Gia - Oprations pr Scond Computation rquirs total of 300 picosconds Additional 20 picosconds to sav rsult in ristr Can must hav clock cycl of at last 320 ps Dlay = Latncy = 320ps = 1/Throuhput

12 3-Way Piplind Vrsion 100 ps 20 ps 100 ps 20 ps 100 ps 20 ps A B C Systm Divid combinational into 3 blocks of 100 ps ach

13 3-Way Piplind Vrsion 100 ps 20 ps 100 ps 20 ps 100 ps 20 ps A B C Dlay = 360 ps Throuhput = 8.33 GOPS Systm Divid combinational into 3 blocks of 100 ps ach Can bin nw opration as soon as prvious on passs throuh sta A. Bin nw opration vry 120 ps Ovrall latncy incrass 360 ps from start to finish

33 GOPS Systm Divid combinational into 3 blocks of 100 ps ach Can bin nw

14 Piplin Diarams Unpiplind OP1 OP2 OP3 Tim Cannot start nw opration until prvious on complts 3-Way Piplind OP1 OP2 OP3 Tim Up to 3 oprations in procss simultanously

15 Opratin a Piplin OP1 OP2 OP Tim 100 ps 20 ps 100 ps 20 ps 100 ps 20 ps A B C

16 Limitations: Nonuniform Dlays ps 20 ps A B C OP1 OP2 OP3 Tim

17 Limitations: Nonuniform Dlays ps 20 ps A B C Dlay = 510 ps Throuhput = 5.88 GOPS OP1 OP2 OP3 Tim Throuhput limitd by slowst sta Othr stas sit idl for much of th tim Challnin to partition systm into balancd stas

18 Limitations: istr Ovrhad

19 Limitations: istr Ovrhad Dlay = 420 ps, Throuhput = GOPS As try to dpn piplin, ovrhad of loadin ristrs bcoms mor sinificant Prcnta of clock cycl spnt loadin ristr: 1-sta piplin: 6.25% 3-sta piplin: 16.67% 6-sta piplin: 28.57% Hih spds of modrn procssor dsins obtaind throuh vry dp piplinin

sinificant Prcnta of clock cycl spnt loadin ristr: 1-sta piplin: 6.

20 What could possibly o wron? 1 irmovl $50, %ax 2 addl %ax, %bx 3 mrmovl 100( %bx ), %dx

21 Data Dpndncis Combinational OP1 OP2 OP3 Tim Systm Each opration dpnds on rsult from prcdin on

22 Data Hazards A B C OP1 OP2 OP3 OP4 Tim sult dos not fd back around in tim for nxt opration Piplinin has chand bhavior of systm

23 Data Dpndncis in Procssors 1 irmovl $50, %ax 2 addl %ax, %bx 3 mrmovl 100( %bx ), %dx sult from on instruction usd as oprand for anothr ad-aftr-writ (AW) dpndncy Vry common in actual prorams Must mak sur our piplin handls ths proprly Gt corrct rsults Minimiz prformanc impact

CS:APP Chapter 4 Computer Architecture. Wrap-Up. William J. Taffe Plymouth State University. using the slides of

CS:APP Chapter 4 Computer Architecture Wrap-Up William J. Taffe Plymouth State University using the slides of Randal E. Bryant Carnegie Mellon University Overview Wrap-Up of PIPE Design Performance analysis