DIGITAL TECHNIC Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COMBINATIONAL LOGIC DEIGN AND ARITHMETIC (THROUGH EXAMPLE) 1st (Autumn) term 2014/2015 COMBINATIONAL LOGIC DEIGN: EXAMPLE AND CAE TUDIE General design procedure Examples Functional units (multiplexer, decoder) as building blocks Logical function unit Mux based shifter Arithmetic circuits 1-bit full adder Addition/subtraction Arithmetic/logic units Multipliers Appendix: Arithmetic logic unit (ALU) 1
YNTHEI UING LOGIC GATE The traditional process of logic synthesis is based on the application of logic gates. Its more modern variant makes use of programmable logic devices too. However in many case it is more advantageous to use a logic synthesis procedure based on the application of logic functional blocks. DIGITAL YNTHEI: BUILDING BLOCK Lower level of abstraction: gates Higher hierarchy: functional building blocks Encoders, decoders Multiplexers, demultiplexers Registers, memories Comparators Adders, etc. (binary arithmetic blocks) Programmable logic devices Technological realization: I/MI circuits 2
FAMILY TREE OF FUNCTIONAL BLOCK functional blocks combinational exor encoder, decoder mux, demux comparator adder ALU code converters tri state buffer etc. sequential register latch counter shift register serial arithmetics etc. DIGITAL COMPONENT High level digital circuit designs are normally made using collections of logic gates referred to as components, rather than using individual logic gates. Levels of integration (numbers of gates) in an integrated circuit (IC): mall scale integration (I): about 10 gates. Medium scale integration (MI): 10 to 100 gates. Large scale integration (LI): 100-1,000 logic gates. Very large scale integration (VLI): 1,000-upward. Ultra large scale integration (ULI): 10,000-upward. Giga large scale Integration (GLI): 100, 000 upward. Ridiculously (?) large scale integration (RLI): 1,000,000 upward. These levels are approximate, but the distinctions are useful in comparing the relative complexity of circuits. 3
What we need to know about an MI circuit? Function: what it does Truth-table: input-output Logic gate diagram: how it does it Packaging (module pin-out): how to build it Dynamic behavior (timing diagram) Applications: where to use it Common MI circuits: programmable logic devices (PLDs) encoder, decoder, exor, comparator, mux, demux, adder, subtractor, arithmetic circuits (adders, multipliers) Arithmetic and Logic Unit (ALU) DECODER APPLICATION: IMPLEMENTING BOOLEAN FUNCTION UING DECODER Any combinational circuit can be constructed using decoders and OR gates! Example: Implement a full adder circuit with a decoder and two OR gates. Recall full adder equations, and let X, Y, and Z be the inputs: (X,Y,Z) = X+Y+Z = m(1,2,4,7) C (X,Y,Z) = m(3, 5, 6, 7). ince there are 3 inputs and a total of 8 minterms, we need a 3-to-8 decoder. 4
IMPLEMENTING A BINARY ADDER UING A DECODER (X,Y,Z) = UM m(1,2,4,7) C(X,Y,Z) = UM m(3,5,6,7) EXAMPE 2: MULTI PURPOE FUNCTION BLOCK Multi-purpose Function Block 3 control inputs to specify operation to perform on operands 2 data inputs for operands 1 output of the same bit-width as operands C0 C1 C2 Function Comments 0 0 0 1 always 1 0 0 1 A + B logical OR 0 1 0 (A B)' logical NAND 0 1 1 A XOR B logical XOR 1 0 0 A XNOR B logical XNOR 1 0 1 A B logical AND 1 1 0 (A + B)' logical NOR 1 1 1 0 always 0 3 control inputs: C0, C1, C2 2 data inputs: A, B 1 output: F 5
IMPLEMENTATION WITH LOGIC GATE C0 C1 C2 A B F 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 0 1 2 3 5 6 7 8 9 10 13 14 16 19 23 24 F = 5 (0-3,5-10,13,14,16,19,23,24) Minimization on 5 variable Karnaugh map: four 4-cubes C0 C1 C2 A B F 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 FORMALIZE THE PROBLEM choose implementation technology 5-variable K-map to discrete gates multiplexer implementation the target operations are pair wise inverse of each other A B A B A B 1 0 0 1 2 3 8:1 MUX 4 5 6 7 2 1 0 C0 C1 C2 F 6
MULTIPLEXER A AN UNIVERAL COMBINATIONAL CIRCUIT From the point of view of output(s) the multiplexer can be considered as a one level combinational circuit. Its characteristics is the fast response time. For the selected input the time delay corresponds to the unit gate delay. Example: Multiplexer based implementation of the XOR function Using a 4-1 Mux to Implement the Majority Function Principle: Use the A and B inputs to select a pair of minterms. The value applied to the MUX input is selected from {0, 1, C, C } to pick the desired behaviour of the minterm pair. 7
EXAMPLE 3: UING MULTIPLEXER TO IMPLEMENT AN ADDER A i B i i C i+1 0 0 C i 0 _ 0 1 C i C i _ 1 0 C i C i Rearrange truth table: 1 0 C i 1 Use A i, B i to select MUX output, connect C i and C i to MUX data inputs. Implement with two 4-to-1 multiplexers and one inverter (to generate C i ) 1-BIT FULL ADDER: MUX IMPLEMENTATION 74153 dual 4-line to 1-line data selector/multiplexer. Two 4/2/1 multiplexers in one package. An inverter is also necessary (e.g. 1/6 7404 hex inverter). 16 8
APPLICATION: MUX BAED HIFTER Draw a 4-bit shifter circuit for the following operation table using only six 2-to-1 multiplexers. Operation: hift left fill with 0 A3 A2 A1 A0 A2 A1 A0 0 hift right fill with 0 A3 A2 A1 A0 0 A3 A2 A1 Rotate left Rotate right A3 A2 A1 A0 A2 A1 A0 A3 A3 A2 A1 A0 A0 A3 A2 A1 17 MUX BAED HIFTER HIFT/ROTATE LEFT/RIGHT 18 9
ARITMETIC CIRCUIT Excellent Examples of Combinational Logic Design Time vs. pace Trade-offs Doing things fast may require more logic and thus more space Example: carry lookahead logic Arithmetic and Logic Units General-purpose building blocks Critical components of processor datapaths Used within most computer instructions CCIRCUIT FOR BINARY ADDITION Half adder (add two 1-bit numbers) um = Ai' Bi + Ai Bi' = Ai xor Bi Cout = Ai Bi Full adder (carry-in to cascade for multi-bit adders) um = Ci xor A xor B Cout = B Ci + A Ci + A B = Ci (A + B) + A B Ai Bi um Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 Ai Bi Cin um Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 10
FULL ADDER IMPLEMENTATION tandard approach 6 gates 2 XORs, 2 ANDs, 2 ORs Alternative implementation 5 gates half adder is an XOR gate and AND gate 2 XORs, 2 ANDs, 1 OR A B Cin A B A B Cin Cout = A B + Cin (A xor B) = A B + B Cin + A Cin Cout A B Cin Half Adder Cout A xor B A B um Half Adder Cout A xor B xor Cin Cin (A xor B) um um Cout ADDER/UBTRACTOR Use an adder to do subtraction thanks to 2s complement representation A B = A + ( B) = A + B' + 1 Control signal selects B or 2s complement of B A3 B3 B3' A2 B2 B2' A1 B1 B1' A0 B0 B0' 0 1 el 0 1 el 0 1 el 0 1 el A B Cout Cin um A B Cout Cin um A B Cout Cin um A B Cout Cin um Add' ubtract 3 2 1 0 Overflow 11
FULL ADDER: GENERATION AND PROPAGATION OF CARRY A B Cin Full adder um Cout C o = A B + (A B)C i or C o = A B + (A + B)C i C o = G + P C i Define G and P auxiliary functions RIPPLE-CARRY ADDER Critical Delay The propagation of carry from low to high order stages Cin @0 A @0 B @N Cin @0 @0 A B late arriving signal @1 @N+1 @1 two gate delays to compute Cout Cout @N+2 A0 B0 A1 B1 A2 B2 0 @2 C1 @2 1 @3 C2 @4 4 stage adder 2 @5 C3 @6 A B Cin A3 B3 3 @7 Cout @8 12
RIPPLE CARRY ADDER The layout of a ripple carry adder is simple, which allows for fast design time, however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit from the previous full adder. From C in to C out 2 gates should be passed through. Ergo a 32-bit adder requires 31 carry computations and the final sum calculation for a total of 31x2 + 1 = 63 gate delays. CARRY LOOK-AHEAD ADDER Carry look-ahead adders reduce the computation time. They work creating propagate and generate signals (P and G) for each bit position, and using them the carries for each position are created. ome multi-bit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carry bypass adder which will determine P and G for each block rather than each bit, and the carry select adder which pre-generates sum and carry values for either possible carry input to the block. 13
FATER ADDITION: CARRY LOOKAHEAD LOGIC Principal layout of carry lookahead adder. CARRY-LOOKAHEAD LOGIC Carry generate: Gi = Ai Bi Must generate carry when A = B = 1 Carry propagate: Pi = Ai xor Bi Carry-in will equal carry-out here um and Cout can be re-expressed in terms of generate/propagate: i = Ai xor Bi xor Ci = Pi xor Ci Ci+1= Ai Bi + Ai Ci + Bi Ci = Ai Bi + Ci (Ai + Bi) = Ai Bi + Ci (Ai xor Bi) = Gi + Ci Pi 14
CARRY-LOOKAHEAD LOGIC Re-express the carry logic as follows: C1 = G0 + P0 C0 C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0 C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0 Each of the carry equations can be implemented with two-level logic All inputs are now directly derived from data inputs and not from intermediate carries this allows computation of all sum outputs to proceed in parallel CARRY-LOOKAHEAD IMPLEMENTATION Adder with propagate and generate outputs Ai Bi Ci Pi @ 1 gate delay i @ 2 gate delays Gi @ 1 gate delay increasingly complex logic for carries C0 P0 G0 C0 P0 P1 G0 P1 G1 C1 C2 C0 P0 P1 P2 G0 P1 P2 G1 P2 G2 C0 P0 P1 P2 P3 G0 P1 P2 C3 P3 G1 P2 P3 G2 P3 G3 C4 15
CARRY LOOKAHEAD CIRCUITRY (a) Circuit for generating the carry-lookahead signals, c1 to c4; (b) One bit slice of the carry-lookahead adder. CARRY-LOOKAHEAD IMPLEMENTATION Carry-lookahead logic generates individual carries ums computed much more quickly in parallel However, cost of carry logic increases with more stages A0 B0 Cin A1 B1 A2 B2 0 @2 C1 @2 A3 B3 1 @3 C2 @4 2 @5 C3 @6 3 @7 Cout @8 Cin A0 B0 C1 @3 A1 B1 C2 @3 A2 B2 C3 @3 A3 B3 0 @2 1 @4 2 @4 3 @4 C4 @3 C4 @3 16
4-BIT CARRY LOOKAHEAD ADDER CIRCUIT carry-out, not c-zero Total 26 gates, c.f. 4 standard full adders 4x6 = 24 gates CARRY LOOKAHEAD ADDER: FEATURE By adding more hardware, we reduced the number of levels in the circuit and sped things up. We can cascade carry lookahead adders, just like ripple carry adders. (We d have to do carry lookahead between the adders too.) How much faster is this? For a 4-bit adder, not much. There are 4 gates in the longest path of a carry lookahead adder, versus 9 gates for a ripple carry adder. But if we do the cascading properly, a 16-bit carry lookahead adder could have only 8 gates in the longest path, as opposed to 33 for a ripple carry adder. Newer CPUs these days use 64-bit adders. That s 12 vs. 129 gates! The delay of a carry lookahead adder grows logarithmically with the size of the adder, while a ripple carry adder s delay grows linearly. The thing to remember about this is the trade-off between complexity and performance. Ripple carry adders are simpler, but slower. Carry lookahead adders are faster but more complex. 17
CARRYLOOKAHEAD ADDER WITH CACDED CARRY-LOOKAHED LOGIC Carry-lookahead adder 4 four-bit adders with internal carry lookahead econd level carry lookahead unit extends lookahead to 16 bits 4 4 4 4 4 4 4 4 A[15-12] B[15-12] 4-bit Adder C12 P G 4 A[11-8] B[11-8] 4-bit Adder C8 P G 4 A[7-4] B[7-4] 4-bit Adder C4 P G 4 A[3-0] B[3-0] 4-bit Adder C0 @0 P G 4 [15-12] @8 @2 @3 [11-8] @8 @5 @2 @3 [7-4] @7 @5 @2 @3 [3-0] @4 @4 @2 @3 C16 C4 @4 P3 G3 C3 P2 G2 C2 P1 G1 C1 Lookahead Carry Unit P3-0 G3-0 @3 @5 P0 G0 C0 C0 @0 CARRY-ELECT ADDER Redundant hardware to make carry calculation go faster Compute two high-order sums in parallel while waiting for carry-in One assuming carry-in is 0 and another assuming carry-in is 1 elect correct result once carry-in is finally computed C8 4-bit adder [7:4] 1 adder high C8 4-bit adder [7:4] 0 adder low five 2:1 mux 1 0 1 0 1 0 1 0 1 0 C4 4-Bit Adder [3:0] C0 C8 7 6 5 4 3 2 1 0 18
CARRY-ELECT ADDER MULTILEVEL CARRY-ELECT ADDER 19
TWO COMPLEMENT ADDER/UBTRACTOR Q = (q 3 q 2 q 1 q 0 ) 2 P = (p 3 p 2 p 1 p 0 ) 2 4A3A2A 1A 4B 3B 2B MUX (74157) 4Y 3Y 2Y 1Y 1B G elect A4 A3 A2 A1 B4 B3 B2 B1 C4 ADDER (7483) 4 3 2 1 C0 elect 0 1 Function R = P + Q R = P + Q + 1 R = (r 4 r 3 r 2 r 1 ) 2 ARITHMETICAL OPERATION IN BCD Many digital systems (processors, computers) can perform the arithmetical operations or a part of them directly on BCD numbers. E.g. the microprocessors can perform BCD addition, several of them subtraction too. Certain special processors can perform BCD multiplication and division too. The BCD addition is reduced to binary addition. The tetrades of the operands are added as binary numbers, and if necessary (illegal codewords or decimal carry is generated during the addition), a systematic correction is performed. 40 20
ADDITION IN NORMAL BCD (8421) CODE If the sum of two tetrades is not larger than 9, the result is valid, no correction is necessary. If the sum of two tetrades is larger than 9, (decimal carry and illegal codeword or pseudotetrade is generated) the result is valid only in binary system and not in BCD. The necessary correction is to add decimal 6 or i.e. binary 0110 to the actual tetrade. The correction should be performed beginning form the least significant tetrade and going upwards step-by-step. 41 FUNCTIONAL DIAGRAM OF A BCD ADDER (1 DIGIT) C4 B3 B2 B1 B0 B3 C4 B2 B1 B0 Binary adder & 1 & 0 0 B3 B2 B1 B0 Binary adder A3 A2 A1 A0 A3 A2 A1 A0 C0 3 2 1 0 A3 A2 A1 A0 C0 3 2 1 0 3 2 1 0 0 0 The first adder adds the two codes corresponding to the k-th decimal place, the second adds 6 if necessary. 42 21
UBTRACTION IN BCD (8421) CODE In BCD as in binary, the subtraction is performed by complementing (the subtrahend) and addition. Generally 9 s complement is used. The circuit generating the 9 s complement can be constructed from common gates or form more complex functional elements. 43 GENERATING 9 COMPLEMENT IN BCD A 3 A 2 A 1 A 0 =1 =1 =1 =1 V 0 0 If V = 0 then X k = A k 4-BIT ADER If V = 1 then 8X 3 +4X 2 +2X 1 +X 0 = = 9 (8A 3 +4A 2 +2A 1 +A 0 ) X 3 X 2 X 1 X 0 22
MULTIPLIER A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. A variety of computer arithmetic techniques can be used to implement a digital multiplier. Most techniques involve computing a set of partial products, and then summing the partial products together. This process is similar to the method taught to primary school children for conducting long multiplication on base-10 integers, but has been modified here for application to a base-2 (binary) numeral system. The first stage of most multipliers involves generating the partial products which is nothing but an array of AND gates. An n-bit by n-nit multiplier requires n 2 AND gates for partial product generation. The partial products are then added to give the final results. THEORY OF MULTIPLICATION Basic Concept multiplicand multiplier * 1101 (13) 1011 (11) 1101 Partial products 1101 0000 1101 10001111 (143) product of two 4-bit numbers is an 8-bit number 23
CMBINATIONAL MULTIPLIER Partial Product Accumulation A3 A2 A1 A0 B3 B2 B1 B0 A2 B0 A2B0 A1 B0 A0 B0 A3 B1 A2 B1 A1 B1 A0 B1 A3 B2 A2 B2 A1 B2 A0 B2 A3 B3 A2 B3 A1 B3 A0 B3 7 6 5 4 3 2 1 0 THE ARRAY MULTIPLIER (4x4 BIT) 24
PARTIAL PRODUCT ACCUMULATION A 3 B 3 A 3 B 2 A 2 B 3 A 3 B 1 A 2 B 2 A 1 B 3 A 3 B 0 A 2 B 1 A 1 B 2 A 0 B 3 A 2 B 0 A 1 B 1 A 0 B 2 A 0 B 1 A 1 B 0 A 0 B 0 F A HA HA HA F A F A F A F A F A F A HA F A 7 6 5 4 3 2 1 0 Note use of parallel carry-outs to form higher order sums 12 Adders, if full adders, this is 6 gates each = 72 gates 16 gates form the partial products total = 88 gates! I REALIZATION OF 4x4 BIT MULTIPLIER 50 25
COMBIATIONAL MULTIPLIER um In X Cin Another Representation of the Circuit Building block: FULL ADDER + AND Y F A A CO B CI Cout um Out A3 A2 A1 A0 B0 C A3 B0 C A2 B0 C A1 B0 C A0 B0 B1 A3 B1 A2 B1 A1 B1 A0 B1 C C C C B2 C A3 B2 C A2 B2 C A1 B2 C A0 B2 B3 A3 B3 A2 B3 A1 B3 A0 B3 C P7 P6 P5 P4 P3 P2 P1 P0 4 x 4 array of building blocks MAKING A 2n-BIT MULTIPLIER UING n-bit MULTIPLIER E.g. in the case of a 8-bit multiplier, it ia possible to partition the problem by splitting both the multiplier and multiplicand into two 4-bit words. N1 = (2 4 H1 + L1) N2 = (2 4 H2 + L2) Multiplying out N1N2 = 2 8 H1H2 + 2 4 (H1L2 + H2L1) + L1L2 26
MAKING A 2n-BIT MULTIPLIER UING n-bit MULTIPLIER Given n-bit multipliers: ynthesize 2n-bit multipliers: MAKING A 2n-BIT MULTIPLIER UING n-bit MULTIPLIER 2n-bit by 2n-bit multiplication: 1. Divide multiplicands into n-bit pieces 2. Form 2n-bit partial products, using n-bit by n-bit multipliers. 3. Align appropriately 4. Add. REGROUP partial products 2 additions rather than 3! Induction: we can use the same structuring principle to build a 4n-bit multiplier from our newly-constructed 2n-bit ones... 27
MULTIPLIER: MODULAR TRUCTURE 8 x 8 bit multiplier built from 4 x 4 bit modules 55 MULTIPLIER: MODULAR TRUCTURE 8 x 8 bit multiplier built from 4 x 4 bit modules Product MB : 0, LB: 15) 56 28
ROM IMPLEMENTED MULTIPLIER Binary multiplication can be achieved by using a ROM as a look-up table. E.g., multiplication of two 4-bit numbers requires a ROM having eight address lines, four of them X4XRX2X1 being allocated to the multiplier, and the remaining four, Y4Y3Y2Y1 to the multiplicand. ince the multiplication of two 4-bit numbers can result in a doublelength product, the ROM should have eight output lines, and a room with capacity of 256 bytes is required. For two 8-bit numbers 2 16 = 65336 memory locations and 16 output lines for the double-length products are required. This requires a ROM of 128 kbytes. For 16-bit multiplication the required ROM capacity is formidable (16 Gbytes!). 8x8 BIT COMBINATIONAL MULTIPLIER 4x4 bit partial products are generated by four 256x8 bit ROMs 29
END OF LECTURE APPENDIX: ARITHMETIC LOGIC UNIT ARITHMETIC LOGIC UNIT (GENERAL) FUNCTIONAL DIAGRAM x y n n Arithmetic Logic hifter hift count OP code CTRL MUX MUX z n Cond. code 60 30
ARITHMETIC LOGIC UNIT: BAIC f0, f1 operation control, 00 - addition 01 - NOT 10 - OR 11 - AND imple ALU, four operations AND, OR, NOT, and addition carried out on two machine words of 2 bits each. DEIGN WITH FUNCTIONAL BLOCK: A CAE TUDY Design a simple four-operation model ALU, capable of performing three logic (XOR, AND, OR) and one arithmetic (UM) operation on two 2-bit numbers/words. The output is a 2-bit number/word with an additional output for the arithmetic carry-out, and it should also have carry-in input to facilitate the cascading of units to handle longer numbers/words. 31
2-BIT ARITHMETIC LOGIC UNIT A1 A0 B1 B0 CIN 2-BIT ALU 1 0 COUT OP1 OP0 2-bit ALU conceptual diagram 63 2-BIT ARITHMETIC LOGIC UNIT FUNCTIONAL DIAGRAM CIN A0 B0 LOGIC UNIT FULL ADDER 3 0 1 M 2 U 3 X OP1 OP0 OUT0 A1 B1 LOGIC UNIT 3 0 1 M 2 U 3 X OUT1 FULL ADDER OP1 OP0 COUT 64 32
2-BIT ALU GATE LEVEL CIRCUIT LOGIC UNIT (0) A B A B A + B CARRY(0)IN 0 FULL ADDER (0) CARRY(0)OUT 65 2-BIT ALU 4-OP: XOR AND OR UM 66 33