# Addressing The problem. When & Where do we encounter Data? The concept of addressing data' in computations. The implications for our machine design(s)

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1 Addressing The problem Objectives:- When & Where do we encounter Data? The concept of addressing data' in computations The implications for our machine design(s) Introducing the stack-machine concept Slide 1

2 What do we mean by data? Data can be held in memory Data is usually organised as 8-bit, 16-bit or 32-bit (Byte, Word, or Double-Word) Data can also be addressed directly as an operand in an instruction - for example ADD A, 03h has an operand 03h Instructions usually operate dyadically - i.e. they require two things. - the example ADD A, 03h has two items to add ( A and 03h ) - Having only one register (A) is not ideal, - It does not match the frequent case of dyadic operations well. - Would more registers be better? Historical interest The 6502 was a successful early CPU in the 70 s, with only an A register. The 6809 emerged later, and had both A and B registers. Let us consider the Jorvick-2 machine design once again. Slide 2

3 Our improved Processor Jorvick 2 :- + Accumulator Detect Zero 1 + Prog Counter bbbb P ppp Opcode Jorvick-2 is an extreme example of an Accumulator machine. All operations use the accumulator (Register A) and a secondary operand - It might be more convenient if there were more registers available Slide 3

4 More Registers - What are the options you may have already encountered the concept of register addressing:- - 3-Register addressing e.g. Add R1,R2, R3-2-Register Addressing e.g. Add R1, R2-1 Register Addressing e.g. Add R1 (to the accumulator) - 0 Register Addressing e.g. Add ( works on a stack) Hardware Impact :- - addressing many registers means Complex and potentially Slower circuitry - addressing fewer registers is generally simpler and faster - But fewer registers makes coding harder, perhaps longer? Short programs on slow machine == big programs on fast machine? Slide 4

5 More Registers A 3-port Register file (most likely to be used in modern CPUs) Consider the example of a 3-port register file of four 8-bit registers :- 2-bit Register Address ZZ R0 R1 R2 R3 2-bit Register Address XX 2-bit Register Address YY Accessing any 3 of 4 registers simultaneously can create design problems. Modern CPU's allow multiple instructions at the same time (ILP), so we may have 3 ports or 3n ports for n simultaneous instructions much worse!. Instructions must contain both the function code (e.g. add, sub etc) and the register addresses. FFFF Rx Ry Rz <- Example of an Instruction 10 BITS Slide 5

6 Less Registers A 1-port Register file the standard Accumulator model The Accumulator model is much simpler, only one register file port is needed, but this is also a data bottleneck and makes ILP very difficult. Acc 2-bit Register Address RR R0 R1 R2 R3 Instructions only contain the function code (e.g. add, sub etc) and one register address, the second register is always the accumulator, FFFF 6 BITS RR <- Example of an Instruction format Slide 6

7 NO Registers The Stack Model The stack (or Zero-Operand) model has no addressable registers, and thus no register file in the traditional sense. TOP NEXT 3RD 4TH Instructions only specify the function code (e.g. add, sub etc). Registers are always TOP and NEXT by default. FFFF 4 BITS <- Example of a Stack Machine Instruction Slide 7

8 Jorvick 3 Adopting a Stack-machine approach:- 3RD But where does the rest of the stack go? NEXT TOP + i0 i1 Detect Zero 1 + Prog Counter L bbb P ppp Opcode J3 is a sort of stack-machine. L bit allows us to load something (a number bbb) onto the stack - But bbb has got shorter and we have introduced new component delays Slide 8

9 J3 Some instruction set examples We can start to see some new instructions when we examine J3 and its circuits. The names are just invented by us to describe operations We can have SET, which pushes a value onto the stack e.g. SET 02h We have ADD, which simply adds two values from the stack together. So we could add two numbers like this :- SET 03h (hex code = B1h) SET 01h (hex code = 91h) ADD (hex code = 01h) However, we cannot do SUB anymore, since our design only has an adder in the Data- Path. Instead we would have to use SET and ADD in the following way:- SET 03h ADD (this will subtract 03h from the top of stack) Slide 9

10 J3 Is this design reaching a Dead-End? - J3 has new features (SET using the L bit, and Branch using P) - But these features have been at the cost of making bbbb and pppp smaller What are the options? - Could we make the instruction bigger use 16 bits instead of 8 bits? - Could we improve the way branches are handled? - Most processors don t combine branches with arithmetic operations - Branches are not as frequent as arithmetic operations (maybe 1:6 ratio) - So 5 out of every 6 instruction bytes have wasted branch bits. - It would be nice to have other instructions - Why not have SUB as well as ADD, also AND and OR are useful - What If I want to DROP something off the stack? Adding these new features is too tricky with J3, we need another technology-shift Slide 10

11 Jorvick 4 The Next Generation of Stack Machine Technology! 3RD NEXT TOP ALU Function Code bits ALU Load Bit i0 i1 Conditional Branch Bit Detect Zero Instruction Decoder 1 + Prog Counter bbbbbbbb Opcode We will start to think about what we can do with our new and more realistic design in the next lecture Slide 11

12 Conclusions We usually need access to two operands at a time An Accumulator can be a bottleneck in this case The alternatives can increase complexity, but are usually unavoidable Stack processors take a different approach, but are not popular at present 8-bits is not enough to control the internal signals of a CPU - we need to look at the alternatives in order to progress Slide 12

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