Karnaugh Maps (K-map) lternate representation of a truth table Red decimal = minterm value Note that is the MS for this minterm numbering djacent squares have distance = 1 Valuable tool for logic minimization pplies most oolean theorems & postulates automatically (when procedure is followed) 0 2-variable form 1 2 3 form 2 1 K-Maps 2 3 1
Karnaugh Maps (K-map) lternate forms of 3-variable K-maps Note end-around adjacency Distance = 1 form 1 form 2 Note: is MS, is LS for minterm numbering 0 1 3 2 7 6 3 2 7 6 2 3 6 7 2 3 6 7 2
K-mapping & Minimization Steps Step 1: generate K-map Put a 1 in all specified minterms Put a 0 in all other boxes (optional) Step 2: group all adjacent 1s without including any 0s ll groups (aka prime implicants) must be rectangular and contain a power-of-2 number of 1s 1, 2, 4, 8, 16, 32, n essential group (aka essential prime implicant) contains at least 1 minterm not included in any other groups given minterm may be included in multiple groups Step 3: define product terms using variables common to all minterms in group Step 4: sum all essential groups plus a minimal set of remaining groups to obtain a minimum SOP 3
K-map Minimization Example Z=,, (1,3,6,7) Recall SOP minterm implementation 8 gates 27 gate I/O K-map results 4 gates gate I/O 0 1 0 3 2 1 0 7 6 1 essential prime implicants Z= + Note: this group not needed since 1s are already covered Z Row value 0 0 0 0 0 0 1 1 0 0 2 1 1 3 1 0 0 0 4 1 0 5 1 1 6 1 1 1 1 7 4
K-map Minimization Goals Larger groups: Smaller product terms Fewer variables in common Smaller ND gates In terms of number of inputs Fewer groups: Fewer product terms Fewer ND gates Smaller OR gate In terms of number of inputs lternate method: Group 0s ould produce fewer and/or smaller product terms Invert output Use NOR instead of OR gate 5
4-variable K-maps Note adjacency of 4 corners as well as sides Variable ordering for this minterm numbering: D D 12 13 8 9 3 2 7 6 15 14 12 13 8 9 3 2 7 6 15 14 form 1 D form 2 6
5-variable K-map Note adjacency between maps when overlayed distance=1 Variable order for this minterm numbering:,,,d,e ( is MS, E is LS) DE 3 2 7 6 DE 16 17 20 21 19 18 23 22 12 13 8 9 15 14 28 29 24 25 31 30 27 26 =0 =1 7
5-variable K-map hanging the variable used to separate maps changes minterm numbering Same variable order for this minterm numbering:,,,d,e ( is MS, E is LS) D 0 2 8 6 4 14 12 D 1 3 9 7 5 15 13 24 26 16 18 30 28 22 20 25 27 17 19 31 29 23 21 E=0 E=1 8
6-variable K-map Variable order for minterm numbers: DEF =0 =1 EF D 12 13 8 9 =0 3 2 7 6 15 14 EF D 32 33 36 37 44 45 40 41 35 34 39 38 47 46 43 42 EF D 16 17 20 21 28 29 24 25 =1 19 18 23 22 31 30 27 26 EF D 48 49 52 53 60 61 56 57 51 50 55 54 63 62 59 58 9
Don t are onditions Sometimes input combinations are of no concern ecause they may not exist Example: D uses only of possible 16 input combinations Since we don t care what the output, we can use these don t care conditions for logic minimization The output for a don t care condition can be either 0 or 1 WE DON T RE!!! Don t are conditions denoted by: X, -, d, 2 X is probably the most often used an also be used to denote inputs Example: = 1X1 = can be a 0 or a 1
Don t are onditions Truth Table K-map Minterm Z=,, (1,3,6,7)+d(2) Maxterm Z=,, (0,4,5)+d(2) Notice Don t ares are same for both minterm & maxterm 0 1 X 3 2 1 0 7 6 1 Z= + Z=+ Z 0 0 0 0 0 1 0 X 1 1 1 0 0 0 1 0 1 1 1 1 1 1 ircuit analysis: G=3 G IO =8 (compared to G=4 & G IO = w/o don t care)
Design Example Hexadecimal to 7-segment display decoder common circuit in calculators 7-segments (-G) to represent digits (0-9 & -F) logic 1 turns on given segment F G E D 7 segments Hex to 7-segment decoder D F F G active (on) segments for a given HEX value = don t care ircuit block diagram 12
HEX to 7-seg Design Example reate truth table from specification F E G D = don t care D E F G 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 X 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1 X 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 13
HEX to 7-seg Design Example Generate K-maps & obtain logic equations D E F G 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 = + + + + + 1 0 0 0 1 1 K-map for output K-map for output = + + + + 14
HEX to 7-seg Design Example K-maps & logic equations for outputs -G 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 X 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 X 1 0 1 1 1 1 1 1 K-map for output K-map for D output K-map for E output K-map for F output = + + + + D = + + + + E = + + + F = + + + + G = + + + + 0 1 1 1 1 1 1 1 1 1 K-map for G output 15
HEX to 7-seg Design Example Remaining steps to complete design: Draw logic diagram (sharing common gates) nalyze for optimization metirc: G, G IO, G del, P del See next page for logic diagram & circuit analysis Simulate circuit for design verification Debug & fix problems when output is incorrect heck truth table against K-map population heck K-map groups against logic equation product terms heck logic equations against schematic Optimize circuit for area and/or performance Use oolean postulates & theorems Re-simulate & verify optimized design 16
# loads on PIs 9 9 9 9 HEX to 7-seg Design Example 1+8 1+7 1+9 1+9 2+3 G1 2+3 G2 G3 G4 G5 G6 G7 G8 G9 2+2 2+2 G G G12 G13 G14 G15 G16 G17 G18 G19 3+2 G20 G21 G22 G23 G24 G25 G26 G27 G1 G2 G3 G4 G17 G18 G6 G7 G5 G G G1 G8 G9 G12 G6 G9 G14 G15 G27 6+0 5+0 4+0 5+0 G1 G5 G19 G20 G21 G22 G23 G24 G25 G26 E G6 G G12 G13 G16 G Prop delay in gates #inputs + # loads 5+0 5+0 5+0 ircuit nalysis G = 38 G IO = 141 G del = 3 P del = 30 worst case path: G1 17 D F