Combinational circuits

Combinational circuits Combinational circuits are stateless The outputs are functions only of the inputs Inputs Combinational circuit Outputs 3 Thursday, September 2, 3

Enabler Circuit (High-level view) Enabler circuit has 2 inputs data (can be several bits, but bit examples for now) enable/disable (i.e., on/off) Enable circuit on : output = data, Enable circuit off : output is zeroed (e.g., output signal is all s) (enabled) (disabled) Enable/Disable Enable/Disable DATA DATA DATA 4 Thursday, September 2, 3

MUX Circuit (High-level) k Data values enter as input Selector chooses which one comes out 2 DATA DATA DATA2 DATA2 DATA3 5 Thursday, September 2, 3

Decoder Circuit (high-level view) No DATA inputs 2 k -bit outputs Selector input chooses which output =, all other outputs = 2 out out out2 out3 6 Thursday, September 2, 3

Building big circuits: Hierarchical design 3-4 A N MX B Big Circuit A B MX N ME E A 2 B 2 A 3 B 3 MX MX N 2 N 3 (a) Design small circuits to be used in a bigger circuit A i Smaller Circuits B i MX N i N N N 2 N 3 ME E (b) (c) 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 7 Thursday, September 2, 3

Notation: Emulating a k-input gate via 2-input Each stage in the circuit cuts # of gates by half k input gate emulated with log2 k depth 2-input gate circuits Same process works for OR, XOR as well 8 Thursday, September 2, 3

Enabler circuits: bit Data input A 3-5 Abbreviated truth table (input listed in the output) XA EN (a) F EN F A EN 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e XA (b) For both enabler circuits above, output is enabled (F=X) only when input ENABLE signal is asserted (EN=). Note the different output when DISABLED F EN F A 9 Thursday, September 2, 3

Decoder-based circuits Converts n-bit input to m-bit output, where n <= m <= 2 n A B C 3:8 decoder Standard Decoder: i th output =, all others =, where i is the binary representation of the input () Thursday, September 2, 3

Decoder-based circuits Converts n-bit input to m-bit output, where n <= m <= 2 n e.g., = (i=5) A B 3:8 decoder C Standard Decoder: i th output =, all others =, where i is the binary representation of the input () Thursday, September 2, 3

Decoder (:2) Internal Design 3-7 A D D D A A D A (a) (b) 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 2 Thursday, September 2, 3

Decoder (2:4) 3-8 A A A D D D 2 D 3 A D A A D A A (a) D 2 A A (b) D 3 A A Standard Decoder: i th output =, all others =, where i is the binary representation of the input 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 3 Thursday, September 2, 3

Hierarchical design of decoder (2:4 decoder) b :2 decoder 'b b 'b'a 'ba a :2 decoder 'a a b'a ba 2:4 decoder Can build 2:4 decoder out of two :2 decoders (and some additional circuitry) 4 Thursday, September 2, 3

Decoder (3:8) Hierarchical design: use small decoders to build bigger decoder 3-9 4 2-input ANDs 8 2-input ANDs A D D A D 2 2-to-4-Line decoder D 3 D 4 A 2 -to-2-line decoders D 5 D 6 D 7 Note: A2 selects whether the 2-to-4 line decoder is active in the top half (A2=) or the bottom (A2=) 3-to-8 Line decoder 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 5 Thursday, September 2, 3

Encoders 6 Inverse of a decoder: converts m-bit input to n-bit output, where n <= m <= 2 n 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e T 3-7 TABLE 3-7 Truth Table for Octal-to-Binary Encoder Inputs Outputs D 7 D 6 D 5 D 4 D 3 D 2 D D A 2 A A Thursday, September 2, 3

Decoders and encoders n{ Decoder }2 n BCD values One-hot encoding n{ n Encoder }2 Note: for Encoders - input is assumed to be just one, the rest s 7 Thursday, September 2, 3

Priority Encoder T 3-8 Designed for any combination of inputs TABLE 3-8 Truth Table of Priority Encoder Inputs Outputs D 3 D 2 D D A A V X X X X X X X X 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 8 Thursday, September 2, 3

General code conversion: a circuit that coverts some inputs to outputs 3-3 a f b e g d c (a) Segment designation (b) Numeric designation for display 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 9 Thursday, September 2, 3

Code conversion Input Output a f e g d b c Va W X Y Z a b c d e f g l 2 3 4 5 6 7 8 9 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 2 Thursday, September 2, 3

f e Code conversion a b g c d e.g., what outputs lights up when input V=4? Input Output Va W X Y Z a b c d e f g l 2 3 4 5 6 7 8 9 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 2 Thursday, September 2, 3

{ Code conversion Input Output a f e b g c d W= For what values does output f light up for? { X X X X X X { Z= Y= { X= Va W X Y Z a b c d e f g l 2 3 4 5 6 7 8 9 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 22 Thursday, September 2, 3

{ Algebra and Circuit for f Y= f = W + YZ + XZ + XY = W + (X+Y)Z + XY W= { X X X X X X { X= { Z= W X f Y Z 23 Thursday, September 2, 3

Multiplexers Combinational circuit that selects binary information from one of many input lines and directs it to one output line n 2 inputs output n selection bits indicate (in binary) which input feeds to the output 24 Thursday, September 2, 3

Multiplexer example I I I2 I3 I 4 I5 I6 I7 I5 25 Thursday, September 2, 3

Multiplexers & Demultiplexers n{ 2 Mux 2^n inputs n { n-bit BCD value output a x x x x x x x a x b x x x x x x b x x c x x x x x c x x x d x x x x d x x x x e x x x e x x x x x f x x f x x x x x x g x g x x x x x x x h h 26 Thursday, September 2, 3

Muxes and demuxes called steering logic Mux Demux merge fork 27 Thursday, September 2, 3

Demultiplexers Demux n }2 n { input n-bit BCD value 2^n outputs a a b b c c d d e e f f g g h h 28 Thursday, September 2, 3

Internal mux organization 3-26 Selector Logic (selects which input flows through ) S Decoder Enabler logic (takes inputs) S 4 2 AND-OR S Decoder S I I Y Or gate passes through the nonzeroed out Ii Y I 2 Only AND gate passes through I 3 AND gates zero out unselected Ii 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 29 Thursday, September 2, 3

Representing Functions with Decoders and MUXes e.g., F = AC + BC A B C minterm F A BC 3-to-8 Decoder 8-to- MUX Decoder: OR minterms for which F should evaluate to A B C MUX: Feed in the value of F for each minterm 3 Thursday, September 2, 3

A Slick MUX trick Can use a smaller MUX with a little trick e.g., F = AC + BC Note for rows paired below, A&B have same values, C iterates between & For the pair of rows, F either equals,, C or C A B C minterm F } } } } F = F = C F = C F = C 4-to- MUX AB AB AB AB A B 3 Thursday, September 2, 3

Slick MUX trick: Example e.g., F = AC + BC + AC A B C minterm F } } } F = F = C F = C } F = C C 4-to- MUX AB AB AB AB A B 32 Thursday, September 2, 3