FPGA Synthesis Example: Counter

Transcription

1 FPGA Synthesis Example: Counter Peter Marwedel Informatik XII, U. Dortmund

2 Gliederung Einführung SystemC Vorlesungen und Programmierung FPGAs - Vorlesungen - VHDL-basierte Konfiguration von FPGAs mit dem XUP VII Pro Entwicklungssystem Algorithmen - Mikroarchitektur-Synthese - Automatensynthese - Logiksynthese - Layoutsynthese Zeitplan 3,5 W ochen 3,5 W ochen 6 Wochen - 2-

3 sw_manuals/xilinx8/download/qst.zip ISE design flow - 3-

4 tutorial Some slides use patched project name Starting a more complex design example Set simulator to ISE for installations without separate Modelsim simulator. - 4-

5 Generated design header tutorial tutorial - 5-

6 Using language templates to define architectural body tutorial Open edit menu - 6-

7 Select simple counter tutorial Select simple counter template and copy tutorial - 7-

8 Copy template to current design tutorial Adapt template as required tutorial - 8-

9 Adding testbench tutorial Add new source to counter tutorial - 9-

10 Set waveform for clock tutorial tutorial

11 Define waveform for other signals tutorial tutorial Click on direction signal to define transitions

12 View generated testbench q

13 Automatically generate expected waveform (1) tutorial Select testbench and check process view q tutorial

14 Automatically generate expected waveform (2) Requires ISE to be specified as the simulator for the project (and simulator must be available)

15 Replacing the original testbench Overwriting initial testbench

16 Automatic or manual comparison? Click on yes/ja in order to compare automatically. Initially unknown

17 Automatic comparison Added when responding 'yes' for the 1st time

18 Behavioral simulation

19 Adding timing constraints (1) Double click on timing constraints

20 Adding timing constraints (2) q

21 Adding timing constraints (3)

22 Add pin constraints Use table from slides fga

23 Synthesis

24 Viewing synthesis results (1) Double click on view RTL

25 Viewing synthesis results (2) Initially, top level module is visible

26 Enter lower level of the hierarchy (1) Right click on module

27 Enter lower level of the hierarchy (2) Oops: no counter register, but separate add/sub component; Additional buffers generated

28 After placement & routing After zooming After double click on place & route; now: check result

29 View result of placement and routing (1) After zooming

30 View result of placement and routing (2) After zooming even more

31 List of used components After enlarging left window

32 Viewing the design summary

33 Estimated power consumption

34 Generate Post-Place & Route Static Timing

35 Checking Timing constraints (1)

36 Checking Timing constraints (2)

37 View routed design (1)

38 View routed design (2)

39 View routed design (3) 4 slices in 1 CLB used

40 Simulate Post-Place & Route HDL Model (1)

41 Simulate Post-Place & Route HDL Model (2) Propagation delays are visible at this level

42 Simulate Post-Place & Route HDL Model (3) Using the measure marker

43 Generation of configuration file

44 Generation of configuration file

45 Summary Fast path through design flow with Xilinx ISE