Design Methodology for Engineering Change Orders (ECOs) in a Flat Physical Standard Cells Based Design Environment
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1 Diploma Thesis Design Methodology for Engineering Change Orders (ECOs) in a Flat Physical Standard Cells Based Design Environment submitted by Anton Klotz
2 Standard-Cells Based Design Flow (1) Picture of a standard cell
3 Standard-Cells Based Design Flow (2) Cells on an ASIC (Netlist)
4 Standard-Cells Based Design Flow (3) Logical Design VHDL, Verilog, Schematic Synthesis RTL -> Gate-Level-Netlist Physical Design Placement, Timing, Routing...
5 Standard-Cells Based Design Flow (4) Flat vs. Hierachical Logical Design Synthesis Synthesis Synthesis Physical Design
6 Physical Design Flow (1) Floorplaning Clock-Tree Design Placement Routing Timing Optmization In-Place-Optimization Static Timing Analysis Release-Checks Check Flow Release
7 What Is an ECO? cells to be exchanged
8 Reasons for an ECO Correction of a logic error during the PD-flow Exchange of timing critical modules during the PD-flow for logic redesign
9 Existing ECO-Solutions (1) (a) (b) 1. PD-Designer sends the current netlist to the logic designer 2. Logic designer inserts manually cells and nets and writes a TCL-script 3. PD-Designer executes the TCL script on his netlist
10 Time consuming and can be faulty Existing ECO-Solutions (2) Disadvantages After passing the netlist to the logic designer, the physical designer is not allowed to change the net and cell names No cloning or inserting of inverters is allowed Remaining false cells increase fan-in, consume area and power Advantages ECO is possible in very late stages of PD (Metal-ECO)
11 Tasks Of the Diploma Thesis (1) Module Change ECO Localization and exchange of a logic module from a netlist after different PD-steps Providing PD-steps on the changed module
12 Tasks Of the Diploma Thesis (2) Minimal ECO Structural analysis of two modules and exchange of different cells for minimizing the amount of exchanged logic
13 Requirements For a Successful ECO (1) Hierarchical Synthesis Modules must be synthesized separately Flattening is the last step of the synthesis module_a module_b top_module_c module_a module_b top_module_c No Boundary Optimization Is Allowed!
14 Requirements For a Successful ECO (2) Every tool marks cells, which are new or changed Every tool writes a log file with executed operations Inserted modules must be flat Number and names of the interface-nets of the module are not allowed to change top-module input module standard output interface-net inter- cell face-net
15 Module Change ECO (1) Main duties: 1. Identification and assignment of cells and nets as part of the module 2. Searching for the interface nets, which are borders of the module 3. Removal of cells and nets, which belong to the module 4. Insertion of the new module in a way, that no inputs and outputs remain open and formal verification reports no logic errors 5. After exchange, all the PD-steps which have been provided on the whole netlist, have to be provided on the module cells only.
16 Module Change ECO (2) Searching for the module-cells (1) core A chk and$1 Name of the cell: core.a.chk.and$1
17 Module Change ECO (3) Searching for the module-cells (2) core core.a1 core.a2 core.a3 core.a4 Several Instances of a Module
18 Module Change ECO (4) Searching for the interface-nets (1) top-module virtual PPIN module top-module DATA_IN(0) flattened module DATA_IN(0) TOP-DATA(0) before flattening after flattening
19 Module Change ECO (5) Searching for the interface-nets (2) output interface-net top-net logic_cell1 logic_cell2 inv2=0 inv2=1 inv1=1 inv2=1 inv1=0 output interface-net logic_cell1 logic_cell2 output interface-net logic_cell1 logic_cell2
20 Module Change ECO (6) Reverse of LLO (1) LLO LLO Reverse
21 Module Change ECO (7) Reverse of LLO (2) Pin Swapping a b a b ineterface_net interface-netnet_a net_a logic_cell net_a logic_cell Find net, which connects to the module Update the entry in the top-nets-file
22 Module Change ECO (8) Removal of Cells and Recovery of the Interface-Nets (1) interface_net top-net cell1_logic cell2_logic cell1_logic cell2_logic
23 Module Change ECO (9) Removal of Cells and Recover of the Interface-Nets (2) cell1_logic cell2_logic interface_net top-net cell1_logic cell2_logic
24 Module Change ECO (10) Some Benchmarks on ET4X4 (1) Number of mov. objects in pre-routing netlist: Number of cells in the module to exchange: Number of instances: 4 Total of cells to exchange: Time Required For ECO Loading the data into ChipBench 13 min Revert LLO-step 33 min Replace instances 3h 11 min Save data 52 min Formal Verification 2h 27 min Total: 8h 26 min
25 Module Change ECO (11) (18) Some Benchmarks on ET4X4 (2) PD-Steps processed with and without ECO PD - Step with ECO without ECO % API-2-VIM 12m 10s 09m 31s +27% Initial Placement 9h 47m 00s 6h 49m 48s +43% First DelayOpt run 5h 18m 22s 17h 53m 36s -70% Adding Netweight to timing critical nets 06m 53s 10m 00s -31% Timing Driven Placement 25h 02m 59s 6h 46m 27s +369% Second DelayOpt run 5h 09m 54s 14h 18m 17s -63% LLO Run 2h 57m 48s 13h 16m 54s -77% Power Vias insertion 26m 57s 38m 53s -30% Routing 10h 55m 52s 100h 23m 04s -89% Total 59h 55m 57s 160h 26m 40s -62%
26 Module Change ECO (12) Some Benchmarks on ET4X4 (3) with ECO without ECO % ECO-Processing 8h 26m 00s - - Scan chain optimization - 06m 41s - nwell Insertion - 57m 11s - Clock Tree Synthesis - 5h 04m 30s - Clock Tree Routing - 3h 09m 58s - PD-Processing for both Netlists 59h 55m 57s 160h 26m 40s -62% Totals 68h 21m 57s 169h 44m 10s -60%
27 Module Change ECO (13) Some Benchmarks on ET4X4 (4) with ECO without ECO s e c after LLO after Clock- Tree Insertion after Routing
28 Minimal ECO (1) affected by the change partly affected by the change not affected by the change not changed modules changed module top-module
29 Minimal ECO (2) Change in Combinatorial Logic unchanged logic changed logic unchanged logic
30 Minimal ECO (3) Structural Analysis
31 Minimal ECO (4) Module After Structural Analysis equal cells not equal cells not checked cells
32 Minimal ECO (5) Exchange of Faulty Cells old module new module
33 Minimal ECO (6) Some Examples (1) Example 1: VHDL-Change: from gate_mask <= gate_and(jump_addr,caplen_mask); to: gate_mask <= gate_and(jump_addr and NOT (capturelength_in = X"03"),caplen_mask); Number of cells in old design 3029 Number of cells in new design 3048 Number of cells, which are not equal 84 (2,7%) Number of cells, which are not checked 123 (4,0%) Percent of cells to exchange 6,7%
34 Minimal ECO (7)
35 Minimal ECO (8) Conclusions Structural Analysis at the current state is not robust enough The approach functions for lot of netlists and is worth to be researched further Methods from Module ECO should be applied for using of Minimal ECO in on PD-processed netlists
36 Last but not Least Thanks to Patrick Haspel and Prof. Brüning for great support during creating of this thesis
37 Further Questions?
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