Chapter 14 Sequential logic, Latches and Flip-Flops

Transcription

1 Chapter 14 Sequential logic, Latches and Flip-Flops Flops

2 Lesson 6 - Flip Flop and -Latch Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

3 - Flip-Flop + ve edge triggered Output Q and Q Q +ve Edge triggered circuit Clock -FF Q Q Q Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

4 - Flip-Flop + ve edge triggered Output Q and Q +ve Edge triggered circuit with clear and preset Clock clear R Preset S PR -FF Q Q Q Q CLR Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

5 - Flip Flop 1. It has edge trigger clock input so that the output state changes only on a clock edge 2. The NANs S input of level clocked SR latch is called - input and R input given input after a not operation on the -input. 3. Second input of both NANs is common 4. Clock input has an additional circuitry to make the transition of Q as per at an instance corresponding to an edge at the clock- input Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

6 - Flip Flop Three input cross coupled NANs Third input of lower NAN connects the Q output Third input of upper NAN connects the Q output. There is no unstable condition in -FF state table Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

7 Clock edge Symbolic representation Up side arrow corresponds +ve edge instance (0 to 1 transition only) Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

8 Timing iagram Refer Text Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

9 = 0 at edge transition (Q = after a delay) Output Q resets to 0 and Q n becomes = 1 after a propagation delay when +ve edge occurs because J = 0 and K = 1 Output Q sets to 1 and Q n becomes = 0 after a propagation delay when +ve edge occurs because J = 1 and K = 0 Q becomes same as after a clock edge. Q n+1 Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

10 +ve edge triggered FF Inputs Output State CLK Q n Q n+1 Q n Q n Q n No change Q n Q n No change X Q same as X X Q n Q n No change X means either 1 or 0 input, Q n+1 means next state after n th clock input Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

11 - Latch (Level clocked ) Output Q and Q Q Level clocked Clock -latch Q Q Q Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

12 - Latch 1. It has level clocking input so that the output state changes only during level 1 2. The NANs S input of level clocked SR latch is called - input and R input given input after a not operation on the -input. 3. Second input of both NANs is common 4. Clock input has no additional circuitry to make the transition of Q as per at level corresponding to 1 at the clock - input Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

13 - Latch (- Transparent latch) There is no unstable condition in - latch state table Q- is transparent to during clock = 1 Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

14 Clock level Symbolic representation corresponds level 1 clocking input Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

15 Timing iagram Refer Text Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

16 = 0 or 1 at clock = 1 transition (Q = after a delay) Output Q resets to 0 and Q n becomes = 1 after a propagation delay during clock = 1 because = 0 Output Q sets to 1 and Q n becomes = 0 after a propagation delay during clock = 1 because = 1 Q becomes same as during clock = 1. Q n+1 Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

17 Latch Inputs Output State Clock Q n+1 Q n+1 X 0 Q n Q n No change Q n Q n+1 X means either 1 or 0 input, Q n+1 means next state after n th clock input Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

18 - Latch with input from Q Output Q and Q Q Level clocked Clock -Latch Q Q 1 Q Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

19 input with feedback from Q n When clock = 1, the output changes 1 to 0 and 0 to 1 at regular intervals with interval = propagation delay of the -latch. We get the pulses at the output When clock = 0, the output freeze, Q cannot change when clock = 0 Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

20 Summary

21 We learnt that in - edge triggered FF: Because K is always complement of J, and input is at J, the output of -flipflops changes to same state as input on edge at -input. [After a period equal to propagation delay.] -latch has no third input at the crosscoupled NANs Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,

22 End of Lesson 6 on - Flip Flop and -Latch

23 THANK YOU Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education,