Data Sheet. HSMP-382x, 482x. Surface Mount RF PIN Switch and Limiter Diodes. Features. Description/Applications

Transcription

1 HSMP-382x, 482x Surface Mount RF PIN Switch and Limiter iodes ata Sheet escription/applications The HSMP-382x series is optimized for switch ing applications where ultra-low resistance is required. The HSMP-482x diode is ideal for limiting and low inductance switching applications up to 1.5 GHz. A SPI model is not available for PIN diodes as SPI does not provide for a key PIN diode characteristic, carrier lifetime. Package Lead ode Identification, SOT-23 (Top View) Features iodes Optimized for: Low urrent Switching Low istortion Attenuating Power Limiting /ircuit Protection Surface Mount SOT-23 and SOT-323 Packages Single and ual Versions Tape and Reel Options Available Low Failure in Time (FIT) Rate [1] Lead-free Note: 1. For more information see the Surface Mount PIN Reliability ata Sheet. Package Lead ode Identification, SOT-323 (Top View) SINGL SRIS UAL ANO #0 OMMON ANO #2 OMMON ATHO HSMP-482B #3 UAL ANO #4 HSMP-4820

2 Absolute Maximum Ratings [1] T = +25 Symbol Parameter Unit SOT-23 SOT-323 I f Forward urrent (1 μs Pulse) Amp 1 1 P IV Peak Inverse Voltage V T j Junction Temperature T stg Storage Temperature -65 to to 150 θjc Thermal Resistance [2] /W Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to the device. 2. T = +25, where T is defined to be the temperature at the package pins where contact is made to the circuit board. lectrical Specifications T = 25 Package Minimum Maximum Maximum Part Number Marking Lead Breakdown Series Resistance Total apacitance HSMP- ode ode onfiguration Voltage V BR (V) R S (Ω) T (pf) 3820 F0 0 Single F2 2 Series 3823 F3 3 ommon Anode 3824 F4 4 ommon athode Test onditions V R = V BR f = 100 MHz f = 1 MHz Measure I F = 10 ma V R = 20 V I R 10 μa High Frequency (Low Inductance, 500 MHz 3 GHz) PIN iodes Minimum Maximum Typical Maximum Typical Part Package Breakdown Series Total Total Total Number Marking Lead Voltage Resistance apacitance apacitance Inductance HSMP- ode ode onfiguration V BR (V) R S (Ω) T (pf) T (pf) L T (nh) 4820 FA A ual Anode B FA A ual Anode Test onditions V R = V BR I F = 10 ma f = 1 MHz f = 1 MHz f = 500 MHz Measure V R = 20 V V R = 0 V 3 GHz I R 10 μa Typical Parameters at T = 25 Part Number Series Resistance arrier Lifetime Reverse Recovery Time Total apacitance HSMP- R S (Ω) τ (ns) T rr (ns) T (pf) 382x V Test onditions f = 100 MHz I F = 10 ma V R = 10 V I F = 10 ma I F = 20 ma 90% Recovery 2

3 Typical Parameters at T = 25 (unless otherwise noted), Single iode I F FORWAR URRNT (ma) V F FORWAR VOLTAG (ma) Figure 1. Forward urrent vs. Forward Voltage. T rr RVRS ROVRY TIM (ns) V R = 2V V R = 5V V R = 10V FORWAR URRNT (ma) Figure 2. Reverse Recovery Time vs. Forward urrent for Various Reverse Voltages. RF RSISTAN (OHMS) I F FORWAR BIAS URRNT (ma) Figure 3. RF Resistance at 25 vs. Forward Bias urrent. APAITAN (pf) V R RVRS VOLTAG (V) Figure 4. apacitance vs. Reverse Voltage. INPUT INTRPT POINT (dbm) iode Mounted as a Series Attenuator in a 50 Ohm Microstrip and Tested at 123 MHz I F FORWAR BIAS URRNT (ma) Figure 5. 2nd Harmonic Input Intercept Point vs. Forward Bias urrent. W POWR OUT (dbm) Measured with external bias return W POWR IN (dbm) 1.5 GHz 1.0 GHz Figure 6. Large Signal Transfer urve of the HSMP-482x Limiter. 40 Typical Applications for Multiple iode Products RF OMMON RF OMMON RF 1 RF 2 RF 1 RF 2 BIAS 1 BIAS 2 BIAS BIAS Figure 7. Simple SPT Switch, Using Only Positive urrent. Figure 8. High Isolation SPT Switch, ual Bias. 3

4 Typical Applications for Multiple iode Products, continued RF OMMON RF OMMON BIAS RF 1 RF 2 RF 1 BIAS RF 2 Figure 9. Switch Using Both Positive and Negative Bias urrent. Figure 10. Very High Isolation SPT Switch, ual Bias. BIAS Figure 11. High Isolation SPST Switch (Repeat ells as Required. Figure 12. Power Limiter Using HSMP-3822 iode Pair. See Application Note 1050 for details. 4

5 Typical Applications for HSMP-482x Low Inductance Series Microstrip Series onnection for HSMP-482x Series In order to take full advantage of the low inductance of the HSMP-482x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in Figure nh 1.5 nh 0.8 pf 0.3 nh 0.3 nh Figure 16. quivalent ircuit. 1 2 Figure 13. Internal onnections. Figure 14. ircuit Layout. Microstrip Shunt onnections for HSMP-482x Series In Figure 15, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the HSMP-482x diode are placed across the resulting gap. This forces the 0.5 nh lead inductance of leads 1 and 2 to appear as part of a low pass filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The 0.3 nh of shunt inductance external to the diode is created by the via holes, and is a good estimate for 0.032" thick material. 50 OHM MIROSTRIP LINS o-planar Waveguide Shunt onnection for HSMP-482x Series o-planar waveguide, with ground on the top side of the printed circuit board, is shown in Figure 17. Since it eliminates the need for via holes to ground, it offers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. See AN1050 for details. Figure 17. ircuit Layout. 0.8 pf o-planar Waveguide Groundplane enter onductor Groundplane 0.75 nh PA ONNT TO GROUN BY TWO VIA HOLS Figure 18. quivalent ircuit. Figure 15. ircuit Layout, HSMP-482x Limiter. 5

6 Assembly Information SOT-323 PB Footprint A recommended PB pad layout for the miniature SOT- 323 (S-70) package is shown in Figure 19 (dimensions are in inches). This layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the performance imensions in inches Figure 19. Recommended PB Pad Layout for Avago s S70 3L/SOT-323 Products. SOT-23 PB Footprint imensions in inches mm Figure 20. Recommended PB Pad Layout for Avago s SOT-23 Products. 6

7 SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. omponents with a low mass, such as the SOT-323/-23 package, will reach solder reflow temperatures faster than those with a greater mass. Avago s diodes have been qualified to the timetemperature profile shown in Figure 21. This profile is representative of an IR reflow type of surface mount assembly process. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. The rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. The maximum temperature in the reflow zone (T MAX ) should not exceed 260. These parameters are typical for a surface mount assembly process for Avago diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder. Tp Ramp-up tp ritical Zone T L to Tp Temperature T L Ts max Ts min ts Preheat t L Ramp-down 25 t 25 to Peak Time Figure 21. Surface Mount Assembly Profile. Lead-Free Reflow Profile Recommendation (IP/J J-ST-020) Reflow Parameter Lead-Free Assembly Average ramp-up rate (Liquidus Temperature (T S(max) to Peak) 3 / second max Preheat Temperature Min (T S(min) ) 150 Temperature Max (T S(max) ) 200 Time (min to max) (t S ) seconds Ts(max) to TL Ramp-up Rate 3 /second max Time maintained above: Temperature (T L ) 217 Time (t L ) seconds Peak Temperature (T P ) /-5 Time within 5 of actual Peak temperature (t P ) seconds Ramp-down Rate 6 /second max Time 25 to Peak Temperature 8 minutes max Note 1: All temperatures refer to topside of the package, measured on the package body surface 7

8 Package imensions Outline 23 (SOT-23) Outline SOT-323 (S-70) e2 e1 e1 XXX 1 XXX 1 e L e L B A1 B Notes: XXX-package marking rawings are not to scale A SYMBOL A A1 B 1 e e1 e2 L IMNSIONS (mm) MIN MAX A1 Notes: XXX-package marking rawings are not to scale A SYMBOL A A1 B 1 e e1 L IMNSIONS (mm) MIN MAX typical 1.30 typical Package haracteristics Lead Material... opper (SOT-323); Alloy 42 (SOT-23) Lead Finish... Tin 100% (Lead-free option) Maximum Soldering Temperature for 5 seconds Minimum Lead Strength... 2 pounds pull Typical Package Inductance...2 nh Typical Package apacitance pf (opposite leads) Ordering Information Specify part number followed by option. For example: HSMP - 382x - XXX Bulk or Tape and Reel Option Part Number; x = Lead ode Surface Mount PIN Option escriptions -BLKG = Bulk, 100 pcs. per antistatic bag -TR1G = Tape and Reel, 3000 devices per 7" reel -TR2G = Tape and Reel, 10,000 devices per 13" reel Tape and Reeling conforms to lectronic Industries RS-481, Taping of Surface Mounted omponents for Automated Placement. 8

9 evice Orientation For Outlines SOT-23/323 RL TOP VIW 4 mm N VIW ARRIR TAP 8 mm AB AB AB AB USR F IRTION OVR TAP Note: "AB" represents package marking code. "" represents date code. Tape imensions and Product Orientation For Outline SOT-23 P P 2 P 0 F W t1 1 9 MAX Ko 8 MAX 13.5 MAX A 0 B 0 AVITY PRFORATION SRIPTION SYMBOL SIZ (mm) SIZ (INHS) LNGTH WITH PTH PITH BOTTOM HOL IAMTR IAMTR PITH POSITION A0 B0 K0 P 1 P ± ± ± ± ± ± ± ± ± ± ± ± ± ARRIR TAP WITH THIKNSS W t ± ± ISTAN BTWN NTRLIN AVITY TO PRFORATION (WITH IRTION) AVITY TO PRFORATION (LNGTH IRTION) F P ± ± ± ±

10 Tape imensions and Product Orientation For Outline SOT-323 P P 0 P 2 F W t 1 (ARRIR TAP THIKNSS) 1 T t (OVR TAP THIKNSS) An K 0 An A 0 B 0 SRIPTION SYMBOL SIZ (mm) SIZ (INHS) AVITY LNGTH WITH PTH PITH BOTTOM HOL IAMTR A 0 B0 K0 P ± ± ± ± ± ± ± ± PRFORATION IAMTR PITH POSITION P ± ± ± ± ± ± ARRIR TAP WITH THIKNSS W t ± ± ± ± OVR TAP WITH TAP THIKNSS Tt 5.4 ± ± ± ± ISTAN AVITY TO PRFORATION (WITH IRTION) F 3.50 ± ± AVITY TO PRFORATION (LNGTH IRTION) P ± ± ANGL FOR SOT-323 (S70-3 LA) An 8 MAX FOR SOT-363 (S70-6 LA) 10 MAX For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. ata subject to change. opyright Avago Technologies. All rights reserved. Obsoletes N AV N - April 24, 2012