One-Bit Adder MIPS. Detecting Overflow. Effects of Overflow. An ALU (arithmetic logic unit) Different Implementations

Transcription

1 MIPS One-Bit Adder it signed numers: two = ten two = + ten two = + ten... two = +,7,8,66 ten two = +,7,8,67 ten two =,7,8,68 ten two =,7,8,67 ten two =,7,8,66 ten... two = ten two = ten two = ten mxint minint Tkes three input its nd genertes two output its Multiple its cn e cscded Detecting Overflow No overflow when dding +ve nd -ve numer No overflow when signs re the sme for sutrction Overflow occurs when the vlue ffects the sign: overflow when dding two +ves yields -ve or, dding two -ves gives +ve or, sutrct -ve from +ve nd get -ve or, sutrct +ve from -ve nd get +ve Consider the opertions A + B, nd A B Cn overflow occur if B is? Cn overflow occur if A is? Effects of Overflow An exception (interrupt) occurs Control jumps to predefined ddress for exception Interrupted ddress is sved for resumption Detils sed on softwre system / lnguge exmple: flight control vs. homework ssignment Don't lwys wnt to detect overflow new MIPS instructions: ddu, ddiu, suu note: ddiu still sign-extends! note: sltu, sltiu for unsigned comprisons An ALU (rithmetic logic unit) Different Implementtions Let's uild n ALU to support ndi nd ori instructions we'll just uild it ALU, nd replicte opertion op res Not esy to decide the est wy to uild something Don't wnt too mny inputs to single gte Don t wnt to hve to go through too mny gtes for our purposes, ese of comprehension is importnt Let's look t -it ALU for ddition: result Sum c out = + c in + c in sum = xor xor c in Possile Implementtion (sum-of-products): 5 How could we uild -it ALU for dd, nd, nd or? How could we uild -it ALU? 6

2 Building it ALU Wht out sutrction ( )? Opertion Opertion ALU Result Two's complement pproch: just negte nd dd. How do we negte? Result ALU C rry O u t Result A very clever solution: Binvert Opertion ALU Result Result ALU Result 7 8 Tiloring the ALU to the MIPS Need to support the set-on-less-thn instruction (slt) rememer: slt is n rithmetic instruction produces if rs < rt nd otherwise use sutrction: (-) < implies < Need to support test for equlity (eq $t5, $t6, $t7) use sutrction: (-) = implies = Supporting slt Cn we figure out the ide? 9 A -it ALU Test for equlity Bnegte Opertion A Ripple crry ALU Two its decide opertion Add/Su AND OR LESS it decide dd/su opertion A crry in it Bit genertes overflow nd set it Notice control lines: = nd = or = dd = sutrct = slt Note: zero is when the result is zero! Result ALU Result ALU Result ALU Result ALU Set Zero Overflow

3 Prolem: ripple crry dder is slow Is -it ALU s fst s -it ALU? Is there more thn one wy to do ddition? two extremes: ripple crry nd sum-of-products Cn you see the ripple? How could you get rid of it? c = c + c + c = c + c + c = c = c + c + c = c = c + c + c = Not fesile! Why? Crry-look-hed dder An pproch in-etween our two extremes Motivtion: If we didn't know the vlue of crry-in, wht could we do? When would we lwys generte crry? g i = i i When would we propgte the crry? p i = i + i Did we get rid of the ripple? c = g + p c c = g + p c c = g +p g +p p c c = g + p c c = g +p g +p p g +p p p c c = g + p c c = g +p g +p p g +p p p g +p p p p c Fesile! Why? A -it crry look-hed dder Use principle to uild igger dders Generte g nd p term for ech it Use g s, p s nd crry in to generte ll C s Also use them to generte lock G nd P CLA principle cn e used recursively ALU P G ALU P G ALU P G C C C pi gi ci + pi + gi + ci + pi + gi + ci + Result-- Crry-lookhed unit Result--7 Result8-- A 6 it dder uses four -it dders It tkes lock g nd p terms nd cin to generte lock crry its out Block crries re used to generte it crries could use ripple crry of -it CLA dders Better: use the CLA principle gin! ALU P G C pi + gi + ci + Result--5 6 Delys in crry look-hed dders -Bit cse Genertion of g nd p: gte dely Genertion of crries (nd G nd P): gte dely Genertion of sum: more gte dely 6-Bit cse Genertion of g nd p: gte dely Genertion of lock G nd P: more gte dely Genertion of lock crries: more gte dely Genertion of it crries: more gte dely Genertion of sum: more gte dely 6-Bit cse gte delys 7 Wht is Relistic Dely Cn we use crry look hed for ll sizes Proly not due to lrge sizes of gte required Wht out 6 it dders Use 8 it locks Eight locks will mke 6 its Wht out its? Compre design using it nd 8 it locks Any cretive thinking? 8

4 Multipliction Multipliction More complicted thn ddition ccomplished vi shifting nd ddition More time nd more re Let's look t versions sed on grde school lgorithm (multiplicnd) x (multiplier) Negtive numers: convert nd multiply Use other etter techniques like Booth s encoding 9 (multiplicnd) x (multiplier) x x x x x x x x (multiplicnd) x (multiplier) x x x x x x x x Multipliction: Implementtion Second Version Strt Strt Multiplicnd Shift left 6 its Multiplier =. Test Multiplier Multiplier = Multiplier =. Test Multiplier Multiplier = 6-it ALU Multiplier its. Add multiplicnd to product nd plce the result in Product register Multiplicnd its. Add multiplicnd to the left hlf of the product nd plce the result in the left hlf of the Product register Product 6 its Write Control test. Shift the Multiplicnd register left it -it ALU Multiplier. Shift the Product register right it its. Shift the Multiplier register right it Product Write Control test. Shift the Multiplier register right it nd repetition? No: < repetitions 6 its nd repetition? No: < repetitions Yes: repetitions Yes: repetitions Done Done Finl Version Multipliction Exmple Strt Itertioplicnd multi- Orignl lgorithm Step Product Initil vlues Multiplicnd its -it ALU Product =. Test Product. Add multiplicnd to the left hlf of the product nd plce the result in the left hlf of the Product register Product = : no opertion : Product : prod = Prod + Mcnd : Product Product 6 its Write Control test. Shift the Product register right it No: < repetitions nd repetition? : prod = Prod + Mcnd : Product Yes: repetitions : no opertion Done : Product

5 Signed Multipliction Let Multiplier e Q[n-:], multiplicnd e M[n-:] Let F = (shift flg) Let result A[n-:] =. For n- steps do A[n-:] = A[n-:] + M[n-:] x Q[] /* dd prtil product */ F<= F.or. (M[n-].nd. Q[]) /* determine shift it */ Shift A nd Q with F, i.e., A[n-:] = A[n-:]; A[n-]=F; Q[n-]=A[]; Q[n-:]=Q[n-:] Do the correction step A[n-:] = A[n-:] - M[n-:] x Q[] /* sutrct prtil product */ Shift A nd Q while retining A[n-] This works lwyse xcepts when oth opernds re.. 5 Booth s Encoding Numers represented using three symols,,, & - Let us consider - in 8 its One representtion is Another possile one - Another exmple + One representtion is Another possile one - We do not explicitly store the sequence Look for trnsition from previous it to next it to is ; to is -; to is ; nd to is Multipliction y,, nd - cn e esily done Add ll prtil results to get the finl nswer 6 Using Booth s Encoding for Multipliction Booth s lgorithm (Neg. multiplier) Convert inry string in Booth s encoded string Multiply y two its t time For n it y n-it multipliction, n/ prtil product Prtil products re signed nd otined y multiplying the multiplicnd y, +, -, +, nd - (ll chieved y shift) Add prtil products to otin the finl result Exmple, multiply (+7) y (-6) Booths encoding of is With -it groupings, multipliction needs to e crried y - nd - (multipliction y -) (multipliction y - nd shift y positions) Add the two prtil products to get (-) s result 7 Itertioplicnd multi- Booth s lgorithm Step Product Initil vlues c: prod = Prod - Mcnd : Product : prod = Prod +M Mcnd : Product c: prod = Prod - Mcnd : Product d: no opertion : Product 8 Crry-Sve Addition Consider dding six set of numers ( its ech in the exmple) The numers re,,,,, (ll positive) One wy is to dd them pir wise, getting three results, nd then dding them gin Other method is dd them three t time y sving crry SUM CARRY 9 Crry-Sve Addition for Multipliction n-it crry-sve dder tke FA time for ny n For n x n it multipliction, n or n/ (for it t time Booth s encoding) prtil products cn e generted For n prtil products, need n/ n-it crry sve dders This yields n/ prtil results Repet this opertion until only prtil results remin Add them using regulr dder to otin n its For n=, you need crry sve dders in eight stges tking 8T time where T is time for one-it full dder You need one crry-propgte/crry-look-hed dder

6 Division Division, First Version Even more complicted cn e ccomplished vi shifting nd ddition/sutrction More time nd more re We will look t versions sed on grde school lgorithm (Dividend) Negtive numers: Even more difficult There re etter techniques, we won t look t them Division, Second Version Division, Finl Version Restoring Division Non-Restoring Division Itertion Divisor Divide lgorithm Step Reminder Initil vlues Shift Rem left : Rem = Rem - Div : Rem < + Div, sll R, R = : Rem = Rem - Div : Rem < + Div, sll R, R = : Rem = Rem - Div : Rem sll R, R = : Rem = Rem - Div : Rem sll R, R = Itertion Divisor Divide lgorithm Step Reminder Initil vlues : Rem = Rem - Div : Rem <,sll R, R = : Rem = Rem + Div : Rem < sll R, R = : Rem = Rem + Div : Rem > sll R, R = : Rem = Rem - Div : Rem > sll R, R = Done shift left hlf of Rem right Done shift left hlf of Rem right 5 6