Design of Combination Circuits

Transcription

1 EGC220 Design of Combination Circuits Baback Izadi Division of Engineering Programs Block diagram of combinational circuit Design of Combinational Logic 1

2 Design Steps From the specification of the circuit, determine the number of inputs and outputs and assign a symbol to each. Derive a truth table, assigning inputs to the left and outputs to the right. Place all possible combination of inputs i.e all 0 s to all 1 s Using the problem definition determine each output. If combinations are left without a specified output, mark them as don t cares. Simplify each output using K-map. Draw a circuit for each output per requirement ie. All NAND, all NOR, AND OR, OR AND, XOR, etc. Design an Adder Design of Combinational Logic 2

3 Design an Adder Design of a full adder Design of Combinational Logic 3

4 Design of Combinational Logic 4

5 Design of Combinational Logic 5

6 Four-bit adder subtractor (with overflow detection) Design of a BCD Excess 3 code convertor. Design a circuit which takes BCD inputs and generate an Excess 3 code. Decimal Digit Input BCD Output Excess-3 A B C D W X Y Z Design of Combinational Logic 6

7 Step 2. Step 2. Design of Combinational Logic 7

8 Design of a multiplier. Design a combinational circuit that multiplies two numbers A and B (A and B are multibit variables). The range of A is from 0 to 2 and the range of B is 1 to 3. Step 2. Step 2. Design of Combinational Logic 8

9 Two-bit by two-bit binary multiplier Design of Combinational Logic 9

10 Parity Generator Even Parity Circuit Design of Combinational Logic 10

11 Design of a 7-Segment Display Driver BCD Input Seven-Segment Decoder A B C D a b c d e f g All other inputs Design of Combinational Logic 11

12 Truth Table of a Three-to-Eight-Line Decoder (1 out of 8 Decoder) 3 8 Decoder Design of Combinational Logic 12

13 2 4 Decoder with one enable line and low active outputs Structural Verilog Description of 2 to 4-Line Decoder Design of Combinational Logic 13

14 Structural Verilog Description of 2 to 4-Line Decoder Design a 4 16 decoder using 3 8 decoders Design of Combinational Logic 14

15 Implementing a full adder using a decoder Truth Table of an 8 3 Encoder Design of Combinational Logic 15

16 Truth Table of a Priority Encoder K-Maps for a priority encoder Design of Combinational Logic 16

17 Four-input priority encoder Parity Checker Design of Combinational Logic 17

18 Two-to-one-line multiplexer Design of Combinational Logic 18

19 Two-to-one-line multiplexer Four-to-one-line multiplexer Design of Combinational Logic 19

20 Mux DeMux Click here for a demonstration. Design a 4 1 Mux using 2 1 Mux s Design of Combinational Logic 20

21 Implementing a Boolean function with a multiplexer Implementing a Boolean function with a multiplexer Design of Combinational Logic 21

22 The Demultiplexer S1 S0 Y3 Y2 Y1 Y Din Din Din Din Design of Combinational Logic 22

23 1 8 DeMux Do the circuits seem familiar? Design of Combinational Logic 23

24 Test 2 Simplification using Boolean logic Simplification using K-map (up to 5 variables) SOP, POS, Standard SOP and POS, Min. SOP and POS Design of combinational circuits Circuit conversion to all NAND or NOR gates Design and use of Multiplexers Demultiplexers Decoders Encoders Graphic symbol for a threestate buffer Design of Combinational Logic 24

25 Gate level schematic for a two-bit greater-than comparator circuit Structural Verilog Description of Two-Bit Greater-Than Circuit Design of Combinational Logic 25

26 Dataflow Verilog Description of Two-Bit Greater-Than Comparator Conditional Dataflow Verilog Description of Two-Bit Greater-Than Circuit Design of Combinational Logic 26

27 Conditional Dataflow Verilog Description of Two-Bit Greater-Than Circuit Using Combinations Behavioral Verilog Description of Two-Bit Greater-Than Circuit Design of Combinational Logic 27

28 Testbench for the Structural Model of the Two-Bit Greater-Than Comparator Propagation Delay for an Inverter Design of Combinational Logic 28

29 Circuit to demonstrate an HDL (Verilog) Module smpl_circuit (A, B, C, D, E) input A, B, C; output D, E; wire w1; and # (30) G1 (w1, A, B); not #10 G2 (E, C); or #(20) G3 (D, w1, E); endmodule Design of Combinational Logic 29

30 Interaction between stimulus and design modules Design of Combinational Logic 30