1. Construction and Mechanism of Operation

Transcription

1 1. Construction and Mechanism of Operation 1.1 Physical Structure The physical structure of an n-type MOS Transistor is shown in Fig This can be seen to be composed of two heavily doped n-type regions, referred to as the source and drain, diffused into a lightly doped p-type substrate, also known as the bulk or body. These are spaced a distance L µm apart and extend across the geometry for a width W µm. Between these two regions, on the surface of the substrate, is deposited an insulating layer of Silicon Dioxide, SiO 2, of thickness t ox, usually between 10 and 50 nm. Finally, this oxide layer is covered with a metal layer (or in more recent years polysilicon) referred to as the gate. Metal connections are then made to the gate, source and drain as terminals. There is normally a connection to the body also and this can be made for individual transistors when required in today s technologies. The three central layers essentially form a parallel plate capacitor and it is this layered structure which gives the device its name, the Metal-Oxide-Semiconductor or MOS Transistor. This capacitor has a capacitance per unit area of C ox = ε ox /t ox. It is the action of creating an electric field across the capacitor to control a conducting channel in the silicon which forms the basis of operation of the device and gives it its full name Metal-Oxide-Semiconductor-Field- Effect-Transistor or MOSFET. The n-type, source and drain regions are reasonably highly doped at a concentration of between and cm -3 while the p-type substrate is lightly doped at a concentration of the order of cm -3. The device shown in Fig. 1.1 is referred to as an n-type MOSFET because, as will be seen, the conducting channel formed is n-type. A p- type MOSFET can be fabricated by diffusing p-type source and drain regions into an n-type substrate. 1.2 Device Operation Voltage sources are normally connected to the n-type MOS transistor as shown in Fig. 1.2(a), which presents a vertical section view through the centre of the device. The voltage connected between gate and source is known as V S while that connected between drain and source is known as V DS. A voltage may also be connected between the source and the body as shown, but very often the source and body terminals are connected together. 1

2 Source S ate Drain D Body B W source n + L drain n + substrate p - Silicon Dioxide S i O 2 Fig.1.1 Physical Structure of the MOSFET 2

3 (i) All Terminals rounded, V S = 0 and V DS = 0 Consider initially the situation where all terminals of the MOSFET, including the body or substrate are connected to ground. Under this condition, p-n junctions will be formed between the source-substrate and drain-substrate regions, which appear essentially back-to-back. Consequently, depletion regions are formed around the source and drain as shown in Fig.1.2(a) and there is an extremely high resistance to current flow between these two terminals. The depletion regions contain positive ions on the n-type side and negative ions on the p- type side of the junctions. As the substrate is more lightly doped, the depletion regions will extend further into the substrate than into the source or drain regions. The energy band diagram for the metal, insulator and semiconductor sandwich is shown in Fig. 1.2(b). When these three materials are brought together, their individual energy bands must realign so that the Fermi level is constant throughout all three materials. This realignment takes place in a different manner to the junction formed in the bipolar transistor, as carriers cannot pass through the insulating dielectric. Instead an electric field is built up across the insulating oxide layer and at its boundary with the substrate. This field is dependent on the difference in the work function of the metal, qφ M and that of the semiconductor, qφ S. The work function is the energy required to remove an electron from the Fermi level in a specific material and is quoted for the material in isolation. The electric field gives rise to the gradient in the energy profile of the oxide from the metal towards the semiconductor as shown. It also gives rise to a bending of the energy levels in the surface region of the semiconductor just below the oxide. Notice that this has the effect of bringing the Fermi level at the doped semiconductor surface closer to the Fermi level of intrinsic silicon. The Fermi potential, φ F, arises from the difference between the Fermi level of the p-type substrate in the MOS structure and that of intrinsic silicon, which is dependent on the doping concentration N A and is given as: φ F = E F E q i = kt ni ln q N This is a negative quantity for p-type silicon. At the surface of the semiconductor this potential is known as the surface potential, φ S, which can be seen to be less than the Fermi potential because of the bending of the energy bands in this region. A 3

4 B V SB = 0V S V S = 0V n + n + V DS = 0V insulating layer SiO 2 D depletion region p- Fig. 1.2(a) Conditions in the MOSFET with all Terminals rounded Metal Oxide Semiconductor + E Field - E C E i E F qφ S qφ F E FS E V Fig. 1.2(b) Energy Band Diagram MOSFET with all Terminals rounded 4

5 (ii) Small Applied ate Bias, V S > 0 and V DS = 0 Next, consider a small positive bias voltage applied to the gate, while the drain-to-source voltage is kept at zero. This will cause positive charge to be accumulated on the gate electrode and will increase the electric field across the insulator. This has the effect of repelling the mobile holes back into the substrate material leaving behind negatively ionised dopant atoms at the surface of the semiconductor to balance the charge accumulated on the gate electrode. In reality, thermally available electrons occupy the vacant energy levels in the dopant acceptor atoms under the influence of the voltage applied to the gate, which holds them in place. This now causes the depletion region to extend along the surface of the semiconductor between the source and drain as shown in Fig. 1.3(a). The energy band diagram under this condition is shown in Fig. 1.3(b). It can be seen that the Fermi levels in the metal and the semiconductor now separate under the influence of the external potential applied to the gate, V S, by an amount equal to qv S. It can also be seen that increased bending of the energy bands at the surface of the semiconductor brings the Fermi level of the substrate nearer to the intrinsic Fermi level. With further increase in the gate voltage, the width of the depletion region at the semiconductor surface increases. Simultaneously, the energy bands continue to bend until the Fermi level in the semiconductor becomes equal to the intrinsic level when φ S = 0. At this point the depletion region under the gate is almost devoid of free charge carriers. (iii) Increased ate Bias, Weak Inversion, V S < V T, V DS = 0 Fig. 1.4(a) shows the situation as the gate voltage is increased further and Fig. 1.4(b) shows how the energy bands in the semiconductor bend further so that the Fermi level at the surface now becomes greater than the intrinsic Fermi level. Under this condition, more electrons are attracted into the region of semiconductor underneath the oxide than are required to ionise the p-type dopant atoms. These electrons are readily supplied by the heavily doped n- type source and drain regions to form a thin conducting layer directly underneath the oxide known as the channel. This process is known as inversion whereby the originally p-type semiconductor now becomes essentially n-type in the channel region, under the influence of the electric field resulting from the applied gate voltage. If a voltage is applied between the drain and the source at this point a current will flow between them. Initially, a channel of very low conductivity is formed and the resulting current is very small and this state is referred to as weak inversion. 5

6 B V SB = 0V S V S > 0V V DS = 0V n + n + D depletion region p- Fig. 1.3(a) Conditions in MOSFET, Small ate Bias V S >0 and V DS = 0 Metal Oxide Semiconductor + E Field - E C E i E F qv S qφ S qφ F E FS E V Fig. 1.3(b) Energy Band Diagram for Small ate Bias V S >0, V DS = 0 6

7 V DS = 0V V SB = 0V V S > 0V B S D n + n + conducting channel p- Fig. 1.4(a) Conditions at Weak Inversion, 0 <V S <V T and V DS = 0 Metal Oxide Semiconductor + E Field - E C qφ F E i qv S qφ S E FS E V E F Fig. 1.4(b) Energy Band Diagram at Weak Inversion, 0<V S < V T,V DS =0 7

8 (iv) Increased ate Bias, Strong Inversion, V S > V T If the gate voltage is increased even further, the n-type conducting channel at the surface of the semiconductor becomes more heavily impregnated with free electrons and therefore becomes more conducting as shown in Fig. 1.5(a). This allows a much greater current to flow between drain and source if a voltage is applied between these two terminals. This state is known as strong inversion. In practice there is a gradual change from the weak inversion state to the strong inversion state, although channel conductivity does rise notably once strong inversion is reached. Further increase in the gate voltage above this value simply leads to increased conductivity of the induced channel and higher levels of current flow between drain and source for a given potential difference between them. 1.3 Threshold Voltage V T For the purposes of device modelling and circuit analysis it is highly desirable to have a definite point marking the transition from weak to strong inversion. The point used is known as the threshold voltage, V T, of the MOSFET. The threshold voltage is defined, for an n-channel device, as the gatesource voltage which causes the n-type conducting channel to have the same concentration of electrons as the p-type substrate has of holes. The energy band diagram of Fig. 1.5(b) shows that at the threshold voltage, the energy bands have bended to bring the Fermi level above the intrinsic Fermi level at the surface of the semiconductor by the same amount as it is below it in the p-type region away from the surface. At this point φ S = -φ F. An expression for the threshold voltage will be derived later. At this point also the depletion region reaches its maximum depth. Any further increase in the gate-source voltage above the threshold value gives negligible increase in the depth of the depletion region. 1.4 CMOS Structures The MOS transistor shown in Fig. 1.1 is an n-channel device, so called because the induced conducting channel is n-type and the charge carriers are electrons. Note that current flow is due entirely to electrons and so this device can be thought of as a unipolar transistor. A p-channel MOS transistor can be fabricated by diffusing heavily doped p-type source and drain regions into a lightly doped n-type substrate. In such a device the induced channel will be p-type and current flow will be entirely due to holes. 8

9 V SB = 0V V S =V T V DS = 0V B S n + n + D p- Fig. 1.5(a) Conditions at Onset of Strong Inversion, V S =V T, V DS = 0 Metal Oxide Semiconductor + E Field - E C qφ F E i qφ S = -qφ F E FS E V qv S E F Fig. 1.5(b) Energy Bands at Onset of Strong Inversion, V S = V T, V DS =0 9

10 CMOS or Complementary-Metal-Oxide-Semiconductor technology combines both p-type and n-type devices on the same chip. Fig. 1.6(a) shows the geometry of a CMOS pair of transistors where the main substrate is p-type and this is used for the n-channel transistors. A lightly doped n-type region, known as an n-well is then diffused sufficiently deeply into the p-type substrate so as to act as a secondary substrate for the p-channel devices. This is known as n-well CMOS technology and its complement p-well technology also exists. Another well-established technology to emerge is twin-tub CMOS technology, shown in Fig. 1.6(b), which uses both p-wells and n- wells diffused into a main substrate that may be of either p-type or n- type material. 10

11 n-channel MOSFET B S D D p-channel MOSFET S B n + n + p + p + n - -well p - substrate Fig. 1.6(a) A CMOS Transistor Pair using n-well Technology n-channel MOSFET p-channel MOSFET B S D D S B n + n + p + p + p-well n-well substrate Fig. 1.6(b) A CMOS Transistor Pair using Twin-Tub Technology 11