The Digital Logic Level
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- Amelia Waters
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1 Gates and Boolean Algebra (1) The Digital Logic Level Chapter 3 (a) A transistor inverter. (b) A NAND gate. (c) A NOR gate. Gates and Boolean Algebra (2) Boolean Algebra The symbols and functional behavior for the five basic gates. (a) Truth table for majority function of three variables. (b) A circuit for (a). 1
2 Circuit Equivalence (1) Circuit Equivalence (2) Construction of (a) NOT, (b) AND, and (c) OR gates using only NAND gates or only NOR gates. Two equivalent functions (a) AB + AC, (b) A(B + C). Circuit Equivalence (3) Circuit Equivalence (4) Some identities of Boolean algebra. Alternative symbols for some gates: (a) NAND, (b) NOR, (c) AND, (d) OR 2
3 Circuit Equivalence (5) Circuit Equivalence (6) (a) The truth table for the XOR function. (b-d) Three circuits for computing it. (a) Electrical characteristics of a device. (b) Positive logic. (c) Negative logic. Integrated Circuits Multiplexers (1) An eight-input multiplexer circuit. An SSI chip containing four gates. 3
4 Multiplexers (2) Decoders (a) An MSI multiplexer. (b) The same multiplexer wired to compute the majority function. A 3-to-8 decoder circuit. Comparators Programmable Logic Arrays A 12-input, 6-output programmable logic array. The little squares represent fuses that can be burned out. A simple 4-bit comparator. 4
5 Shifters Adders (1) (a) (b) A 1-bit left/right shifter. (a) A truth table for 1-bit addition. (b) A circuit for a half adder. Adders (2) Arithmetic Logic Units (1) A 1-bit ALU. (a) Truth table for a full adder. (b) Circuit for a full adder. 5
6 Arithmetic Logic Units (2) Clocks Eight 1-bit ALU slices connected to make an 8-bit ALU. The enables and invert signals are not shown for simplicity. (a) A clock. (b) The timing diagram for the clock. (c) Generation of an asymmetric clock. Latches (1) Latches (2) (a) NOR latch in state 0. (b) NOR latch in state 1. (c) Truth table for NOR. A clocked SR latch. 6
7 Latches (3) Flip-Flops (1) A clocked D latch. (a) A pulse generator. (b) Timing at four points in the circuit. Flip-Flops (2) Flip-Flops (3) A D flip-flop. D latches and flip-flops. 7
8 Flip-Flops (4) Flip-Flops (5) Dual D flip-flop. Octal flip-flop. Memory Organization (1) Memory Organization (2) Logic diagram for a 4 x 3 memory. Each row is one of the four 3-bit words. (a) A noninverting buffer. (b) Effect of (a) when control is high. (c) Effect of (a) when control is low. (d) An inverting buffer. 8
9 Memory Chips (1) Memory Chips (2) Two ways of organizing a 4-Mbit memory chip. Two ways of organizing a 512 Mbit memory chip. Nonvolatile Memory Chips CPU Chips A comparison of various memory types. The logical pinout of a generic CPU. The arrows indicate input signals and output signals. The short diagonal lines indicate that multiple pins are used. For a specific CPU, a number will be given to tell how many. 9
10 Computer Buses (1) Computer Buses (2) A computer system with multiple buses. Examples of bus masters and slaves. Bus Width Bus Clocking (1) Growth of an Address bus over time. Read timing on a synchronous bus. 10
11 Bus Clocking (2) Asynchronous Buses Specification of some critical times. Operation of an asynchronous bus. Bus Arbitration (1) Bus Arbitration (2) (a) A centralized one-level bus arbiter using daisy chaining. (b) The same arbiter, but with two levels. Decentralized bus arbitration. 11
12 Bus Operations (1) Bus Operations (2) A block transfer. Use of the 8259A interrupt controller. The Pentium 4 The Pentium 4 s Logical Pinout The Pentium 4 physical pinout. Logical pinout of the Pentium 4. Names in upper case are the office are the official Intel names for individual signals. Names in mixed case are groups of related signals or signal descriptions. 12
13 Pipelining on the Pentium 4 s Memory Bus The UltraSPARC III (1) Pipelining requests on the Pentium 4 s memory bus. The UltraSPARC III CPU chip. The UltraSPARC III (2) The 8051 (1) The main features of the core of an UltraSPARC III system. Physical pinout of the
14 The 8051 (2) The ISA Bus Logical pinout of the The PC/AT bus has two components, the original PC part and the new part. The PCI Bus (1) The PCI Bus (2) Architecture of an early Pentium system. The thicker buses have more bandwidth than the thinner ones but the figure is not to scale. The bus structure of a modern Pentium 4. 14
15 PCI Bus Arbitration PCI Bus Signals(1) The PCI bus uses a centralized bus arbiter. Mandatory PCI bus signals. PCI Bus Signals(2) PCI Bus Transactions Optional PCI bus signals. Examples of 32-bit PCI bus transactions. The first three cycles are used for a read operation, then an idle cycle, and then three cycles for a write operation. 15
16 PCI Express PCI Express Protocol Stack A typical PCI Express system. (a) The PCI Express protocol stack. (b) The format of a packet. The Universal Serial Bus PIO Chips The USB root hub sends out frames every 1.00 ms. An 8255A PIO chip. 16
17 Address Decoding (1) Address Decoding (2) Location of the EPROM, RAM, and PIO in our 64 KB address space. Full address decoding. Address Decoding (3) Partial address decoding. 17
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CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop