Register Transfer Level Design with Verilog

Transcription

1 Register Transfer Level Design with Verilog Adapted from Z. Navabi Portions Copyright Z. Navabi, Register Transfer Level Design with Verilog 2.1 RT Level Design Control/data partitioning Data part Control part 2.2 Elements of Verilog Hardware modules Primitive instantiations Assign statements Condition expression Procedural blocks Module instantiations 2 1

2 Register Transfer Level Design with Verilog 2.3 Component Description in Verilog Data components Controllers 2.4 Testbenches A simple tester Tasks and functions 2.5 Summary 3 RT Level Design RT level design: Taking a high level description of a design Partitioning Coming up with an architecture Designing the bussing structure Describing and implementing various components of the architecture Steps in RT level design: Control/Data Partitioning Data Part Design Control Part Design 4 2

3 RT Level Design RT Level Design Control/data Partitioning Data Part Control Part 5 Control/Data Partitioning RT Level Design Control/data Partitioning Data Part Control Part 6 3

4 Control/Data Partitioning RT Level Design Data Inputs DataPath Reg Flags & status Opcode Control Control Outputs Data flow Control signals Data Outputs Control Inputs 7 Data Part RT Level Design Control/data Partitioning Data Part Control Part 8 4

5 Data Part Data Inputs Data Outputs Reg DataPath Flags & status Opcode Data flow Control signals 9 Data Part Output Signals: module DataPath Going to the control (DataInput, DataOutput, Flags, Opcodes, part, provide flags ControlSignals); and status of the data input [15:0] DataInputs; output [15:0] DataOutputs; Control Signals: output Flags,...; Inputs to data part, output Opcodes,...; sent to the data components input ControlSignals,...; and busses // instantiation of data components //... // interconnection of data components // bussing specification Control Signals for the module busses: Select the sources DataPath Module and routing of data from one data component to another 10 5

6 Data Part module DataComponent (DataIn, DataOut,, ControlSignals); Data Component: Shows how the component uses its input control signals to perform various operations on its data inputs input [7:0] DataIn; output [7:0] DataOut; input ControlSignals; // Deping on ControlSignals // Operate on DataIn and // Produce DataOut module Partial Verilog Code of a Data Component 11 Control Part RT Level Design Control/data Partitioning Data Part Control Part 12 6

7 Control Part Control Flags & status Opcode Data flow Control signals Consists of one or more state machines to keep the state of the circuit. Control Outputs Control Inputs Makes decisions as to when and what control signals to issue deping on its state. 13 Control Part module ControlUnit (Flags, Opcodes, ExternalControls, ControlSignals); input Flags,...; Takes control input Opcodes,...; inputs from the input ExternalControls,...; Data Part output ControlSignals; // Based on inputs decide : // What control signals to issue, // and what next state to take module Outline of a Controller 14 7

8 Elements of Verilog We discuss basic constructs of Verilog language for describing a hardware module. 15 Elements of Verilog Hardware Modules Primitive Instantiations Condition Expression Assign Statements Procedural Blocks Module Instantiations 16 8

9 Hardware Modules Hardware Modules Primitive Instantiations Condition Expression Assign Statements Procedural Blocks Module Instantiations 17 Keyword module Hardware Modules module : The Main Component of Verilog module module-name Variables, wires, and List of ports; module parameters Declarations are declared.... Functional specification of module... Keyword module module Module Specifications 18 9

10 Hardware Modules There is more than one way to describe a Module in Verilog. May correspond to descriptions at various levels of abstraction or to various levels of detail of the functionality of a module. Descriptions of the same module need not behave in exactly the same way nor is it required that all descriptions describe a behavior correctly. We discuss basic constructs of Verilog language for a hardware module description. We show a small example and several alternative ways to describe it in Verilog. 19 Primitive Instantiations Hardware Modules Primitive Instantiations Condition Expression Assign Statements Procedural Blocks Module Instantiations 20 10

11 Primitive Instantiations a a_sel Logic Gates called Primitives s b s_bar b_sel w A Multiplexer Using Basic Logic Gates 21 Primitive Instantiations module MultiplexerA (input a, b, s, output w); wire a_sel, b_sel,, s_bar; not U1 (s_bar, s); and U2 (a_sel( a_sel,, a, s_bar); Instantiation of Primitives and U3 (b_sel( b_sel,, b, s); or U4 (w, a_sel, b_sel); module Primitive Instantiations 22 11

12 Assign Statements Hardware Modules Primitive Instantiations Condition Expression Assign Statements Procedural Blocks Module Instantiations 23 Assign Statements Continuously drives w with the right hand side expression module MultiplexerB (input( a, b, s, output w); assign w = (a & ~s) (b & s); module Using Boolean Assign Statement and Boolean expressions to describe the logic 24 12

13 Condition Expression Hardware Modules Primitive Instantiations Condition Expression Assign Statements Procedural Blocks Module Instantiations 25 Condition Expression Can be used when the operation of a unit is too complex to be described by Boolean expressions module MultiplexerC (input( a, b, s, output w); assign w = s? b : a; module Assign Statement and Condition Operator Useful in describing a behavior in a very compact way Very Effective in describing complex functionalities 26 13

14 Procedural Blocks Hardware Modules Primitive Instantiations Condition Expression Assign Statements Procedural Blocks Module Instantiations 27 Procedural Blocks always statement Sensitivity list module MultiplexerD (input( a, b, s, output w); reg w; b, s) begin if (s) w = b; else w = a; Can if-else be used when the module operation statement of a unit is too complex to be Procedural Statement described by Boolean or conditional expressions 28 14

15 Module Instantiations Hardware Modules Primitive Instantiations Condition Expression Assign Statements Procedural Blocks Module Instantiations 29 Module Instantiations module ANDOR (input( i1, i2, i3, i4, output y); ANDOR assign y = (i1 & i2) (i3 & i4); module is module defined // module MultiplexerE (input( a, b, s, output w); wire s_bar; not U1 (s_bar, s); ANDOR U2 (a, s_bar, s, b, w); ANDOR module module is Module Instantiation instantiated 30 15

16 Module Instantiations a s b i1 i2 i3 i4 ANDOR y w Multiplexer Using ANDOR 31 Component Description in Verilog Component Description Data Components Controllers 32 16

17 Data Components Component Description Data Components Controllers 33 Data Components Data Components Multiplexer Flip-Flop Counter Full-Adder Shift-Register ALU Interconnections 34 17

18 Multiplexer Data Components Multiplexer Flip-Flop Counter Full-Adder Shift-Register ALU Interconnections 35 Multiplexer Defines a Time Unit of 1 ns and Time Precision of 100 ps. `timescale 1ns/100ps module Mux8 (input( sel, input [7:0] data1, data0, output [7:0] bus1); assign #6 bus1 = sel? data1 : data0; module Octal 2-to-1 MUX A 6-ns Delay is specified for all values assigned to bus1 Selects its 8-bit data0 or data1 input deping on its sel input

19 Flip-Flop Data Components Multiplexer Flip-Flop Counter Full-Adder Shift-Register ALU Interconnections 37 Flip-Flop Flip-Flops are A used Software-Like in data part for Procedural flags and data Coding storage Style Synchronous `timescale 1ns/100ps reset inputi Flip-Flop The Body of always triggers on the module Flop (reset, din, clk, qout); statement is falling edge of input reset, din, clk; A executed Signal declared at the as a clk Input reg output qout; to be capable of negative edge of holding the its values reg qout; clk signal between clock edges clk) begin if (reset) qout <= #8 1'b0; else qout <= #8 din; module A Non-blocking An 8-ns Assignment Flip-Flop Description Delay 38 19

20 Counter Data Components Multiplexer Flip-Flop Counter Full-Adder Shift-Register ALU Interconnections 39 Counter Counters are used in A 4-bit modulo-16 data part for registering Counter data, accessing memory or queues and register `timescale 4-bit 1ns/100ps stacks Register module Counter4 (input( reset, clk, output [3:0] count); reg [3:0] count; clk) begin Constant Definition if (reset) count <= #3 4'b00_00; else count <= #5 count + 1; When count module reaches 1111, Counter Verilog Code the next count taken is

21 Full-Adder Data Components Multiplexer Flip-Flop Counter Full-Adder Shift-Register ALU Interconnections 41 A combinational circuit All Changes `timescale 1ns/100ps Occur after 5 ns Full-Adder Full-Adders are used in data part for building Carry-Chain adders module fulladder (input a, b, cin, output sum, cout); assign #5 sum = a ^ b ^ cin; assign #3 cout = (a & b) (a & cin) (b & cin); module All Changes Occur after 3 ns One Full-Adder delay for Verilog Code every output: tplh and tphl 42 21

22 Shift-Register Data Components Multiplexer Flip-Flop Counter Full-Adder Shift-Register ALU Interconnections 43 2 Mode inputs m[1:0] form a `timescale 2-bit number 1ns/100ps Shift-Register An 8-bit Universal Shift Register module ShiftRegister8 (input sl, sr, clk, input Case Statement [7:0] ParIn, input [1:0] m, output With 4 reg case-alternatives [7:0] ParOut); and default Value clk) begin case (m) m=0 : Does Nothing 0: ParOut <= ParOut; 1: ParOut <= {sl{ sl, ParOut [7:1]}; 2: ParOut <= {ParOut{ [6:0], sr}; m=1,2: : Shifts Right 3: ParOut <= ParIn; and Left default: ParOut <= 8'bX; case m=3 : Loads its Parallel input into the register module 44 22

23 Shift-Register (Continued) `timescale 1ns/100ps module ShiftRegister8 (input sl, sr, clk, input [7:0] ParIn, input [1:0] m, output reg [7:0] ParOut); Shift Right: The SL input is clk) begin concatenated to case (m) the left of ParOut 0: ParOut <= ParOut; 1: ParOut <= {sl{ sl, ParOut [7:1]}; 2: ParOut <= {ParOut{ [6:0], sr}; 3: ParOut <= ParIn; default: ParOut <= 8'bX; Shifting the case ParOut to the left module 45 ALU Data Components Multiplexer Flip-Flop Counter Full-Adder Shift-Register ALU Interconnections 46 23

24 `timescale 1ns/100ps ALU module ALU8 (input( [7:0] left, right, input [1:0] mode, output reg [7:0] ALUout); right, mode) begin case (mode) 0: ALUout = left + right; 1: ALUout = left - right; 2: ALUout = left & right; 3: ALUout = left right; default: ALUout = 8'bX; case module 2-bit mode Input to select one of its 4 functions Add Subtract AND OR An 8-bit ALU 47 ALU (Continued) The Declaration of ALUout both as `timescale 1ns/100ps output and reg: Because of module ALU8 (input( [7:0] left, right, assigning it within input [1:0] mode, a Procedural Block output reg [7:0] ALUout); right, mode) begin case (mode) Blocking 0: ALUout = left + right; Assignments 1: ALUout = left - right; 2: ALUout = left & right; 3: ALUout = left right; default: ALUout = 8'bX; default alternative case puts all Xs on ALUOut if mode containsc module anything but 1s s and 0s An 8-bit ALU 48 24

25 Interconnections Data Components Multiplexer Flip-Flop Counter Full-Adder Shift-Register ALU Interconnections 49 Interconnections Inbus Aside Bside 8 8 select_source Mux8 and ALU examples forming a Partial Hardware 8 8 ABinput Function 8 Outbus Partial Hardware Using MUX8 and ALU 50 25

26 Interconnections Instantiation of ALU8 and MUX8 A Set of parenthesis enclose port connections to the instantiated modules ALU8 U1 (.left(inbus),.right(abinput),.mode(function),.aluout(outbus) ); Mux8 U2 (.sel(select_source),.data1(aside),.data0(bside),.bus1 (ABinput( ABinput)); u1 Verilog and u2 : Code of The Partial Hardware Example Instance Names 51 Interconnections An Alternative format of port connection The actual ports of the instantiated components are excluded ALU8 U1 ( Inbus, ABinput,, function, Outbus ); Mux8 U2 ( select_source,, Aside, Bside, ABinput ); Ordered Port Connection The list of local signals in the same order as their connecting ports 52 26

27 Controllers Component Description Data Components Controllers 53 Controllers Decisions Based on :Inputs, Outputs,State Issue Control Signal Set Next State Controller Outline Go to Next State 54 27

28 Controllers Controller: Is wired into data part to control its flow of data. The inputs to it controller determine its next states and outputs. Monitors its inputs and makes decisions as to when and what output signals to assert. Keeps the history of circuit data by switching to appropriate states. Two examples to illustrate the features of Verilog for describing state machines: Synchronizer Sequence Detector 55 Controllers Controllers Synchronizer Sequence Detector 56 28

29 Synchronizer Controllers Synchronizer Synthesizer Sequence Detector 57 Synchronizer Clk adata synched Synchronizing adata 58 29

30 Synchronizer `timescale 1ns/100ps module Synchronizer (input( clk, adata, output reg synched); clk) if (adata( == 0) synched <= 0; If a 1 is Detected on else synched <= 1; adata on the rising module edge of clock, synched becomes 1 and A Simple Synchronization Circuit remains 1 for at least one clock period 59 Sequence Detector Controllers Synthesizer Sequence Detector 60 30

31 Sequence Detector Searches on it s a input for the 110 Sequence a If 110 is detected on a, then w gets 1, else w gets 0. When the sequence is detected, the w Output becomes 1 and stays 1 for a complete clock cycle w clk State Machine Description 61 A Moore Machine Sequence Detector Initial State reset Sequence Detector Sequence Detector State Machine 0 States are named: s0, s1, s2, s3 1 1 S0 S1 S2 S The State in which the 110 sequence is detected. It Takes at least 3 clock periods to get to the s3 state 62 31

32 Sequence Detector module Detector110 (input( a, clk,, reset, output w); parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11; reg [1:0] current; clk) begin if (reset) current = s0; else case (current) s0: if (a) current <= s1; else current <= s0; s1: if (a) current <= s2; else current <= s0; s2: if (a) current <= s2; else current <= s3; s3: if (a) current <= s1; else current <= s0; case assign w = (current == s3)? 1 : 0; module Verilog Code for 110 Detector 63 Sequence Detector module Detector110 (input( a, clk,, reset, output w); parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11; Behavioral Description of the State Machine reg [1:0] current; A 2-bit Register clk) begin if (reset) current = s0; else Parameter declaration defines constants s0, s1, s2, s3 Verilog Code for 110 Detector 64 32

33 Sequence Detector clk) begin if-else statement if (reset) current = s0; checks for reset else At the case (current) Absence of s0: if (a) current <= s1; else current <= s0; a 1 on reset s1: if (a) current <= s2; else current <= s0; s2: if (a) current <= s2; else current <= s3; s3: if (a) current <= s1; else current <= s0; case The 4 Case-alternatives each correspond to a Verilog Code for 110 Detector state of state machine 65 Sequence Detector s1 0 s1: a=1 if (a) a=0 s0 0 s2 0 else current <= s2; current <= s0; State Transitions on Corresponding Verilog Code 66 33

34 Sequence Detector Outside of the always Block: A combinational circuit assign w = (current == s3)? 1 : 0; module Verilog Code for 110 Detector Assigns a 1 to w output when Machine Reaches to s3 State 67 Testbenches Testbenches A Simple Tester Tasks And Functions 68 34

35 A Simple Tester Testbenches A Simple Tester Tasks And Functions 69 `timescale 1ns/100ps A Simple Tester module Detector110Tester; reg aa,, clock, rst; wire ww; Detector110 UUT (aa( aa,, clock, rst, ww); initial begin aa = 0; clock = 0; rst = 1; initial repeat (44) #7 clock = ~clock; initial repeat (15) #23 aa = ~aa~ aa; initial begin #31 rst = 1; #23 rst = 0; ww) if (ww == 1) $display ("A 1 was detected on w at time = %t", $time); module Testbench for Detector

36 Begins with the module keyword `timescale 1ns/100ps A Simple Tester Unlike other descriptions doesn t t have input or output ports module Detector110Tester; reg aa,, clock, Outputs rst; are Inputs are Declared as reg wire ww; declared as wire Detector110 UUT (aa( aa,, clock, rst, ww); The Instantiation of Detector110 Module Testbench for Detector A Simple Tester initial statement drives test values into the variables connected to the An initial statement: A inputs. sequential statement that... runs once and stops... when it reaches its last initial begin statement aa = 0; clock = 0; rst = 1; initial repeat (44) #7 clock = ~clock; initial repeat (15) #23 aa = ~aa~ aa; All Initial Blocks initial begin Start at Time 0 and #31 rst = 1; Run Concurrently #23 rst = 0; Testbench for Detector

37 A Simple Tester Repeats 44 times of... complementing the For... Initializing clock input with 7ns the Input Signals initial begin delay, generates a periodic aa = 0; clock = 0; rst = 1; signal on clock initial repeat (44) #7 clock = ~clock; initial repeat (15) #23 aa = ~aa~ aa; initial begin #31 rst = 1; Signal aa is also #23 rst = 0; assigned a periodic signal, with a different frequency Testbench for Waits Detector ns before assigning 1 to rst 73 A Simple Tester always Block Wakes up when ww Changes Reports the Times at which... the ww Variable... becomes 1 ww) if (ww == 1) $display ("A 1 was detected on w at time = %t", $time); module This Note Will Appear Testbench for Detector110 in the Simulation A Verilog Environment s System Task Window: Console or Transcript 74 37

38 Tasks And Functions Testbenches A Simple Tester Tasks And Functions 75 Tasks And Functions Verilog Tasks and Functions: System tasks for Input, Output, Display, and Timing Checks User defined tasks and functions Tasks: Can represent a sub module within a Verilog module Begins with a task keyword Its body can only consist of sequential statements like if-else and case Functions: Can be used for corresponding to hardware entities May be used for writing structured codes Applications: Representation of Boolean functions, data and code conversion, and input and output formatting 76 38

39 Funky parallelism Hardware is inherently parallel FPGA = Fine-grained massively parallel computer Verilog = Funky parallel programming language 77 Verilog tips and traps 78 39

40 Constants: 32 bits, decimal wire [7:0] foo = 127; // synthesis warning! wire [7:0] foo = 8 d127; 8 wire [7:0] foo = 8 b ; 8 wire [7:0] foo = 8 hff; 8 wire [7:0] foo = 8 hff; 8 watch out: 1010 looks like 4 b1010! 4 79 Truncation wire [7:0] a = 8 hab; 8 wire b; // oops! forgot width wire [7:0] c; assign b = a; // synthesis warning if lucky. assign c = a; 80 40

41 reg vs.. wire wire f; reg g, h; assign f = a & b; clk) g <= a & b; h = a & b; 81 (blocking) = vs.. <= (non-blocking) Simple rule: If you want sequential logic, use clk) ) with <=. (non-blocking) If you want combinational logic, use with =. (blocking) 82 41

42 (blocking) = vs.. <= (non-blocking) clk) begin f <= a + b; g <= f + c; clk) begin f = a + b; g = f + c; // a + b + c always@(posedge clk) begin f2 <= f1; f3 <= f2; f4 = f3; f5 = f4; // f5 = f3!! f7 = f6; f6 = f5; 83 Verilog Stratified Event Queue [1] Region 1: Active Events Most events except those explicitly in other regions Includes $display system tasks Region 2: Inactive Events Processed after all active events #0 delay events (bad!( bad!) Region 3: Non-blocking Assign Update Events Evaluation previously performed Update is after all active and inactive events complete Region 4: Monitor Events Caused by $monitor and $strobe system tasks Region 5: Future Events Occurs at some future simulation time Includes future events of other regions Other regions only contain events for CURRENT simulation time

43 Verilog Stratified Event Queue [2] within a block, blocking assignments, are in order Incomplete sensitivity lists or b) // it s s or, not f = a & b; f = a & b; always f = a & b; Just use always@(*) for combinational logic 86 43

44 Blocking and non-blocking assignments Blocking assignments (Q = A) Variable is assigned immediately New value is used by subsequent statements Non-blocking assignments (Q <= A) Variable is assigned after all scheduled statements are executed Value to be assigned is computed but saved for later Example: Swap CLK) begin temp = B; B = A; A = temp; CLK) begin A <= B; B <= A; 87 Blocking and non-blocking assignments reg B, C, D; clk) begin B = A; C = B; D = C; reg B, C, D; clk) begin B <= A; C <= B; D <= C; 88 44

45 The following code executes incorrectly One block executes first Loses previous value of variable CLK) begin A = B; Swap Non-blocking assignment fixes this Both blocks are scheduled by posedge CLK CLK) begin B = A; CLK) begin A <= B; CLK) begin B <= A; 89 Parallel versus serial execution assign statements are implicitly parallel = means continuous assignment Example assign E = A & D; assign A = B & C; A and E change if B changes always blocks execute in parallel clock) Procedural block internals not necessarily parallel = is a blocking assignment (sequential) <= <= is a nonblocking assignment (parallel) Examples of procedures: always, function,, etc. B C A D E 90 45