PRM and VTM Parallel Array Operation

Transcription

1 APPLICATION NOTE AN:002 M and V Parallel Array Operaion Joe Aguilar VI Chip Applicaions Engineering February 2014 Conens Page Inroducion 1 High-Level Guidelines 1 Sizing he Resisor 4 Arrays of Six or 5 More Ms Sysem Consideraions 7 X Ms o Y Vs 7 Layou Consideraions 9 Table 1. Adapive Loop Ms Inroducion VI Chip M Regulaors and V Curren Mulipliers can be configured o allow for greaer sysem power capaciy. When Ms and Vs are conneced in an array, he array can suppor higher curren and power han a circui wih a single M and V. In an array, he Ms and Vs mus all be of he same ype and model number. This noe covers Adapive Loop Ms (M-AL) and he requiremens for using hem in parallel. A lis of applicable Ms is shown in Table 1. Par Number Vin (V) Vou (V) Oupu Power (W) Package MP028x036M12AL 28 ( ) 36 (26-50) 120 Full Chip MR028A036M012FP 28 ( ) 36 (26-50) 120 VI Brick P024x048T12AL 24 (18-36) 48 (26-55) 120 Full Chip 024A480x012xP 24 (18-36) 48 (26-55) 120 Full VI Brick P036x048T12AL 36 (18-60) 48 (26-55) 120 Full Chip 036A480x012xP 36 (18-60) 48 (26-55) 120 Full VI Brick P045x048T17AL [1] 45 (38-55) 48 (26-55) 170 Full Chip 045A480x017xP [1] 45 (38-55) 48 (26-55) 170 Full VI Brick P045x048T32AL [1] 45 (38-55) 48 (26-55) 320 Full Chip 045A480x032xP [1] 45 (38-55) 48 (26-55) 320 Full VI Brick P048x048T12AL [1] 48 (36-75) 48 (26-55) 120 Full Chip 048A480x012xP [1] 48 (36-75) 48 (26-55) 120 Full VI Brick P048x048x24AL [1] 48 (36-75) 48 (26-55) 240 Full Chip 048A480x024xP [1] 48 (36-75) 48 (26-55) 240 Full VI Brick [1] No recommended for new designs. High-Level Guidelines A maser-slave configuraion is used for arrays of Ms. Up o five Ms of he same ype may be placed in an array o expand he power capaciy of he sysem. In connecing Ms in an array, one of he Ms is designaed as he maser: i akes conrol pin inpus and drives he bus in an acive conrol loop. Addiional Ms in he array ac as slave powerrains only; hey use he signal as he conrol inpu. Referring o he schemaic shown in Figure 1, he following guidelines mus be considered for he resuling sysem o sar up and operae properly, o avoid oversress on he circui, and o avoid exceeding he absolue maximum raings of he componens. AN:002 vicorpower.com Applicaions Engineering: Page 1

2 High-Level Guidelines (Con.) One M mus be designaed as a maser by configuring he device conrol pins for inended operaion. All oher Ms mus be designaed as slave Ms by ying pins o. Vicor recommends making his connecion hrough a 0 Ω resisor for roubleshooing purposes. All Ms in he array mus have he pins conneced ogeher. They mus be powered from a common power source, so ha he inpu volage o each M is he same. An independen fuse for each M connecion is required o mainain safey cerificaions (see Inpu Fuse Recommendaions secion of he M daashee). An independen inducor for each M and connecion is required when used in an array, o conrol circulaing currens among he Ms and reduce he impac of bea frequencies. M pins mus be conneced ogeher for sarup synchronizaion. Exernal capaciance on he bus is no permied. pins mus be conneced ogeher o enable sharing. The bandwidh requiremens of are low enough ha he bus can be considered a lumped elemen, raher han a ransmission line, and so sar connecions o he maser M wih subs, as well as daisy chain connecions are permied. A resisor should be conneced beween maser Ms and pins in close proximiy o he module for noise immuniy. The value of he resisor depends on he number of Ms in he array. Please refer o he Sizing he Resisor secion for more informaion. The race lengh beween devices should be minimized o avoid inroducing addiional noise and he bus should no be roued under any M. The pin of a M is he reference for all conrol signals inernal o he device. The pins of all Ms in he array should connec ogeher o form an ND reference as shown in Figure 1. If here are significan offses beween connecions, series resisors may be needed o preven excessive curren in he pins. Refer o he Layou Consideraions secion for more informaion. The pin of each M in he array mus be conneced o one or wo pins of a V, or i mus be erminaed o wih a 1kΩ resisor. The pin mus no be lef un-erminaed for any M. When operaing wihin an array, he maser M is raed for full power while he slave Ms are de-raed o he array raed power and curren values provided for slave operaion. For Ms covered in his applicaion noe, slaves should be de-raed by 35%. The number of Ms required o achieve a given array capaciy mus consider hese de-raings o avoid oversressing any M in he array (See Table 2). Use of rimming wihin an array is no permied and all pins mus be bypassed wih a capacior beween he and pins of each device. Slave devices mus have a resisor beween he and pins o ensure he maximum volage is no exceeded. Vicor recommends using he same value resisor on slaves as he maser M. The Adapive Loop design procedures will generally hold for any array, alhough some parameers mus adjused based on he number of Ms and Vs in he sysem. All Ms in he array mus be enabled and disabled synchronously. Enabling and disabling Ms independenly wihin an array (phase shedding) is no permied. Arrays of six or more Ms may be possible hrough use of exernal circuiry. Please refer o Arrays of Six or More Ms o follow. AN:002 vicorpower.com Applicaions Engineering: Page 2

3 Figure 1. M-V Parallel Configuraion (up o five Ms) R M 1 MASTER V 1 V OUT C R R V Sar Up Pulse and Temperaure Feedback C OUT R R V IN F 1 L IN 1 VF: 26 V o 55 V L F 1 C F 1 SEC_ C IN IMARY M 2 SLAVE V 2 R V Sar Up Pulse F 2 L IN 2 L F 2 C F 2 IMARY ~ ~~ ~ ~ ~ ~ M N SLAVE V N R V Sar Up Pulse F L N IN N L F N C F N IMARY SEC_ AN:002 vicorpower.com Applicaions Engineering: Page 3

4 Sizing he Resisor The pin of he M is conneced o a bi-direcional buffer. The volage on he conroller side of he buffer deermines he iming of he power rain (and ulimaely he power delivered o he load). When designaed as a maser, an inernal error amplifier generaes he conrol signal; he buffer is configured as an oupu ha drives he bus. In slave mode, he inernal error amplifier is disabled, and he buffer is configured as an inpu which sinks curren. As more slaves are added o he bus, he required drive curren from he maser increases. The drive capaciy of he maser will be exceeded wih five or more slaves. Figure 2. Curren Pah from Maser o Slave Gae Drive V OUT Enable Type 2 compensaion 1 ma max Modulaor Error amplifier + V REF I R_INT Maser Gae Drive Enable Type 2 compensaion Modulaor I R_INT Error + amplifier (Disabled) Slave For noise immuniy, an exernal resisor R should be conneced beween maser Ms and pins in close proximiy o he module. R should be sized based on he number of slaves; i should be made as small as possible aking ino accoun he maximum drive curren of he maser M which is limied o 1 ma. Equaion 1 and Table 2 show how o calculae he value of he exernal resisor. The inernal nework (R -NT and I ) sinks a maximum of 250 µa and he maximum volage is 7 V. Equaion 1. Value of Exernal Resisor R _EXT = 7 V 1 ma N SLAVES (250 µa) AN:002 vicorpower.com Applicaions Engineering: Page 4

5 Table 2. Calculaed Values of Resisor Array Size Array raed Power and Curren relaive o daashee raing N SLAVES R _EXT 2 165% kω 3 230% kω 4 295% kω 5 360% 4 (OPEN) 6 425% 5 Exernal buffer required Arrays of Six or More Ms As menioned above, he pin is specified o drive up o four slaves for a maximum array size of five Ms. An array of six or more Ms requires exernal circuiry. The recommended circui is illusraed in Figure 3. An opamp buffer circui is used in order o limi he loading on he maser pin. The and pins of he maser M can be used o supply he opamp provided ha he raings of he pin are no exceeded. A 10 kω resisor should be conneced beween maser Ms and pins. The characerisics of he opamp used for he buffer should be carefully considered. The seleced opamp should mee or exceed he specificaions of he amplifier inernal o he M. Table 3 summarizes he key characerisics of he opamp and minimum performance crieria. In addiion o a buffer, he bus requires a pull-up o an exernal source o ensure proper sarup. The maser M pin can be used provided he connecion is made hrough a diode. Diode (D1) and pull up resisor (R ) are illusraed in Figure 3. During normal operaion, is a conrol inpu for he Adapive Loop circuiry; herefore a low leakage diode such as he 1N4148 mus be used o ensure ha normal operaion and accuracy are no impaced. Please conac Vicor Applicaions for assisance wih arrays of six or more Ms. Table 3. Operaional Amplifier Performance Crieria Parameer Minimum Requiremens Noes is limied o 5 ma. The oal curren draw including Supply Curren See Noes opamp supply curren mus be considered in order o ensure he maximum curren is no exceeded. Drive Curren See Noes Mus be capable of driving he bus aking ino accoun he curren draw of he slave devices. Bypass Capaciance 0.1 µf Mus be capable of operaing wih 0.1 µf or less o say wihin limiaions of. Inpu Offse Volage 1 mv Any offses beween he maser and slave volages will lead o sharing error. The inpu offse volage of he opamp mus be minimized. Slew Rae 10 V/µs Mus be capable of racking he maser signal wih Gain Bandwidh 10 MHz minimal delay and over/undershoo during ransiens. Oupu 7.4 V Should have rail-o-rail oupu capabiliy and mus be High Volage capable of driving he bus over he full range of Oupu 0.4 V 0.4 V o 7.4 V. Low Volage AN:002 vicorpower.com Applicaions Engineering: Page 5

6 Figure 3. M-V Parallel Configuraion (six or more Ms) 1 Pullup R 1N Buffer Maser Signal R C R R M 1 MASTER 1 V Sar Up Pulse and Temperaure Feedback V 1 VOUT C OUT Buffered Signal 10k R V IN F 1 L IN 1 VF: 26 V o 55 V L F 1 C F 1 SEC_ C IN IMARY M 2 SLAVE V 2 R V Sar Up Pulse F 2 L IN 2 L F 2 C F 2 IMARY ~ ~ ~ ~ ~ ~ ~ M N SLAVE V N R V Sar Up Pulse F L N IN N L F N C F N IMARY SEC_ AN:002 vicorpower.com Applicaions Engineering: Page 6

7 Sysem Consideraions When used wih a V, he pin provides a pulse of bias power for he V during sar up. During normal operaion, he maser M uses he connecion for emperaure compensaion of he adapive loop (his is done hrough an inernal PTC resisor on he V s pin). In he slave Ms, is only used for sarup; i has no effec on he adapive loop since slave Ms use as heir conrol inpu. In general, he of each M is conneced o only one V. If necessary, can be conneced o up o wo Vs, aking ino accoun he resisance of he second pin when calculaing he loop componen values. Circuis wih unequal numbers of Ms and Vs are discussed in he following secion (see AN:024 for more informaion on adapive loop seings). All V fauls lach he V powerrain off. Inpu power o he sysem as a whole mus be recycled or he Ms should be disabled and enabled by way of heir bussed connecion in order o resar he sysem. Vicor recommends ha he volage on he facorized bus be permied o reurn o zero before he M is re-enabled. Oherwise he sof sar of he sysem may be compromised. The pins of all Ms in he array should be conneced ogeher o synchronize hem during sarup. The M pin does no have pull down capabiliy. If a slave M fauls, he array will coninue o operae (wih reduced curren and power capaciy) unil he maser deecs a faul and iniiaes a resar. Faul synchronizaion beween Ms and Vs is possible hrough he use of exernal circuiry. Please conac Vicor Applicaions Engineering for addiional informaion. X Ms o Y Vs Whenever possible, each M should be conneced o one V. Should he number of Ms be unequal o he number of Vs, here are cerain hings o consider during seup. Wih a greaer number of Ms han Vs, here will be Ms lef wih an un-erminaed pin. These pins mus be erminaed wih a 1 kω resisor. In he case ha a greaer number of Vs han Ms are being used, a M pin can drive up o wo Vs wihou he need for exernal circuiry as menioned above. Connecing an addiional V o he maser will impac he adapive loop seings and emperaure compensaion since a second PTC resisor is in parallel wih he firs (see AN:024 for more informaion on adapive loop seings). Driving more han wo Vs requires exernal circuiry; please conac Vicor Applicaions Engineering for more deails on his configuraion. AN:002 vicorpower.com Applicaions Engineering: Page 7

8 Figure 4. Two M / One V Schemaic R M 1 MASTER V 1 V OUT C R R V Sar Up Pulse and Temperaure Feedback C OUT R R V IN F 1 L IN 1 VF: 26 V o 55 V L F 1 C F 1 C IN IMARY SEC_ M 2 SLAVE R 1k F 2 L IN 2 L F 2 C F 2 Figure 5. One M / Two V Schemaic R M 1 MASTER V 1 V OUT C R R V Sar Up Pulse and Temperaure Feedback C OUT R V IN L F 1 C IN VF: 26 V o 55 V C F 1 SEC_ IMARY V 2 IMARY SEC_ AN:002 vicorpower.com Applicaions Engineering: Page 8

9 Layou Consideraions Please reference applicaion noe AN:005 FPA Prined Circui Board Layou Guidelines, for a deailed discussion on B layou. Applicaion noe AN:005 deails board layou recommendaions using VI Chip componens, wih deails on good power connecions, reducing EMI, and shielding of conrol signals and echniques o reference hem o. Avoid rouing conrol signals (,, ec.) direcly underneah he M. I is criical ha all conrol signals (aside from ) are referenced o, boh for rouing and for pulldown and bypassing purposes. provides conrol and feedback from a V, and mus be referenced o of he M ( of he V). connecs inernally o -IN and is he reference for all conrol signals wihin he device. In mos applicaions where Ms are mouned o he same B, he pins can be conneced ogeher o form an ND reference node for he array. Curren in he ND reference node should be minimized and ND should no be ied o any oher ground in he sysem including -IN. In cases where here is significan resisance beween each pin and he common supply reurn, volage offses can be generaed beween he M pins, which could cause curren flow in he ND node on he board. Care should be aken o minimize hese offses; oherwise series resisors may be needed beween each slave pin and he ND node roued on he board, o ensure he maximum curren is no exceeded. A slave resisor of 1 Ω migh be ypical, bu please conac Vicor Applicaions Engineering for more deails. The M senses is oupu curren wih an inernal shun conneced from o. In an array, hese resisors are in parallel. For bes operaion, he currens in hese sense resisors should be roughly equal, and he reurn currens among Ms should be balanced hrough proper layou. and canno be conneced ogeher and mus be reaed as separae nes. Oherwise he inernal shun will be bypassed, disabling curren sensing wihin he device. AN:002 vicorpower.com Applicaions Engineering: Page 9

10 Revision Hisory Revision Dae Descripion Page Number(s) /2014 Updaed recommendaions and forma All /2014 Updaed Figure 4 8 The Power Behind Performance Rev /14 vicorpower.com Applicaions Engineering: Page 10