Intended audience The application note addresses experienced hardware engineers who have already basic knowledge of the 6EDL family 2 nd generation.

Transcription

1 EiceDRIVER Tips & Tricks for RCIN and ITRIP 6EDL family - 2nd generaion Applicaion Noe AN Abou his documen Scope and purpose The RCIN and ITRIP funcions srongly help o reduce he sysem cos. However, he funcions as hey are available do have limiaions in some applicaions. This applicaion noe helps o undersand he funcion more in deail and give applicaion suppor how o overcome hese limiaions. Inended audience The applicaion noe addresses experienced hardware engineers who have already basic knowledge of he 6EDL family 2 nd generaion. Table of Conens 1 Inroducion Overcoming he large olerance of he RCIN iming Overcome he high rigger level of he ITRIP funcion... 7 Applicaion Noe AN <Revision 2>, < > AN

2 Inroducion 1 Inroducion The 6EDL family 2 nd generaion is a family of versaile and robus driver ICs. This applicaion noe is relaed o he family s members given in Table 1 Table 1 Members of 6ED family 2 nd generaion Sales code conrol inpu HIN1,2,3 and LIN1,2,3 UVLO hreshold Boosrap diode Package Opimal for 6EDL04I06NT negaive logic 12.1V/10.2V Yes DSO28 IGBT 6EDL04I06PT posiive logic 12.1V/10.2V Yes DSO28 IGBT 6EDL04N06PT / 6EDL04N02PR 6ED003L06-F2 / 6ED003L02-F2 posiive logic 8.9V/8.0V Yes DSO28 / TSSOP28 negaive logic 12.1V/10.2V No DSO28 / TSSOP28 MOSFET IGBT, replacemen of 1 s generaion The RCIN and ITRIP funcions srongly help o reduce he sysem cos. However, he funcions as hey are available do have limiaions in some applicaions. This applicaion noe helps o undersand he funcions in deep deail and gives applicaion suppor on how o overcome he limiaions. I is mandaory for he undersanding of his documen o carefully read he daashee [1] and he 6EDL echnical descripion [2]. Applicaion Noe AN <Revision 2>, < >

3 Overcoming he large olerance of he RCIN iming 2 Overcoming he large olerance of he RCIN iming This secion describes how he raher large olerance of he RCIN iming can be overcome. 2.1 Applicaion problem The RCIN funcion ([1], [2]) of he 6EDL family 2 nd generaion provides an inegraed curren source as depiced in a) of Figure 1. I usually allows skipping an exernal pull-up resisor. The olerance of his curren source can be derived from a specific daashee parameer according o b) in Figure 1. a) COM R SH VSS ITRIP RCIN V Z =10.5V V IT,TH+ = 0.445V Comp. V DD2 8V I RCIN b) INPUT NOISE FILTER S Q SET DOMINANT LATCH R V RCIN,TH = 5.2V C RCin NMOS V RCIN,HYS = 2.0V VSS C F 6ED family 2nd generaion V CC curren source R ON,RCIN V IT,HYS = 70mV o /FAULT o inpu signal logic Figure 1 a) RCIN circui b) Daashee excerp of he faul clear ime FLTCLR The faul clear ime FLTCLR specifies he charging ime of he RCIN capacior C RCIN in he daashee. The RCIN capacior is charged from he inernal curren source for his parameer. Therefore, he olerance of he curren source can be derived from he parameer olerances. This means ha he olerance of he curren source is approx. 52 % and + 58 %. Such olerances may be no accepable especially for faul clear imes FLTCLR which are longer han 5 ms. For simplificaion, i is assumed in he following secions ha he inernal curren source has a olerance of ± 50%. 2.2 Applicaion soluion The siuaion which is described in secion 2.1 can be solved by applying an addiional, highly accurae curren source o charge he capacior C RCIN according o Figure 2. This can be implemened by a pull-up resisor R RCIN o a volage V pu. The pull-up resisor mus have a olerance of 1%. The pull-up curren needs o be large enough o une he overall charging curren ino a suiable design window. Applicaion Noe AN <Revision 2>, < >

4 Overcoming he large olerance of he RCIN iming Two assumpions are made: The pull-up curren I RRCIN and he value I RCIN of he inegraed curren source according o Figure 2 are small wih respec o he iniial curren ampliude during discharge of he capacior C RCIN. Therefore, only he capacior C RCIN dominaes he discharge process VCC COM I RRCIN R SH VSS R RCin ITRIP C F RCIN 6ED family 2nd generaion V Z =10.5V V CC V IT,TH+ = 0.445V Comp. V DD2 8V I RCIN V IT,HYS = 70mV curren source INPUT NOISE FILTER o inpu signal logic S Q SET DOMINANT LATCH R V pu D Z C RCin NMOS R ON,RCIN V RCIN,TH = 5.2V V RCIN,HYS = 2.0V VSS o /FAULT Figure 2 Improved RCIN circui Targe power ransisor is a IKD06N60RF I is described in [2] ha he pull-up resisor bears he risk ha he capacior C RCIN is no discharged fas enough, so ha he IC also does no reach he ITRIP lach sae. This is shown in he righ par of Figure 3. I leads o an occurrence of muliple shor circui or overcurren shu-down evens wihou geing ino he faul clear sae. Therefore, he maximum discharge ime mus remain smaller han he minimum shu down propagaion delay discharge = R on,rcin C RCIN ln V h,rcin V pu < T ITRIP,min + d(off),min The evaluaion of his equaion shows ha i can easily ge criical o use he IC s supply volage V VCC as he pull-up volage: discharge (C RCIN = 10 nf, V pu = 15 V) = 0.62 µs < 400 ns ns = 506 ns (2) This means ha he shu down occurs earlier han he discharge reaches he laching level of 3.2 V. Thus, he IC does no reach he safe faul clear sae and acivaes is oupus again. This is shown in he righ par of Figure 3. (1) v ITRIP V VDD v RCIN I SC v ge, i T v IT,TH+ discharge 3.2V ITRIP + d(off) 5.2V FLTCLR PWM v ITRIP V VDD 3.2V v RCIN I SC v ge, i T Figure 3 lef: suiable RCIN iming wih safe faul clear sae righ: bad RCIN iming wihou reaching faul clear sae Applicaion Noe AN <Revision 2>, < >

5 Overcoming he large olerance of he RCIN iming So boh, charging and discharging of he capacior C RCIN mus be carefully evaluaed in order o achieve a suiable and precise RCIN iming according o he lef par of Figure 3. A lower pull-up volage can be necessary and can be achieved by implemening a sabilized volage source by means of a biased zener diode according o he red pars in Figure 2. I is assumed ha he curren hrough R RCIN is consan during he charging and discharging unil he relevan hresholds are reached. The pull-up curren hrough resisor R RCIN is superposed ono he curren I RCIN of he inegraed curren source. The inegraed curren source delivers I RCIN = 2.8 µa wih a olerance of Tol incs. The oal arge olerance of he charging curren is Tol. The charging curren hrough R RCIN can be calculaed o be I RRCIN,charge = ( Tol incs Tol 1) I RCIN The charging curren hrough R RCIN leads o he corresponding resisance value of R RCIN = V pu I RRCIN,charge (4) The calculaed faul clear ime including a pull-up resisor R RCIN is depiced in Figure 4. The arge capacior value C * RCIN can be calculaed by scaling wih he raio of a given faul clear ime and he arge faul clear ime FLTCLR,arge using he calculaed value of R RCIN in equaion (4). The applicaion example in secion 2.3 explains his procedure in deail. The scaling calculaion is (3) C RCIN = FLTCLR,arge RRCIN,CRCIN C RCIN (5) Now, equaion (1) can be execued and verified by using C* RCIN. 2.3 Applicaion example 100 ms 10 FLTCLR kw OPEN R RCIN Figure 4 Resuling faul clear ime of C RCIN in combinaion wih R RCIN. The shadowed area shows he faul clear ime wihou R RCIN Applicaion Noe AN <Revision 2>, < >

6 Overcoming he large olerance of he RCIN iming The applicaion example should achieve he arge behavior including: Overall olerance Tol < 20 % Faul clear ime FLTCLR = 10 ms The pull-up volage is V pu = 8.2 V Execuing equaion (3) wih he arge condiions resuls in I charge,rrcin = ( Tol incs Tol The relaed pull-up resisance is The closes mach of he E24 series of resisors is a value of 2.0 MW. The scaling of he read ou value in Figure 4 is now he nex procedure sep. The readou value of he dashed purple line a R RCIN = 2.0 MW and C RCIN = 10 nf is FLTCLR = 8.5 ms. The calculaed capaciance C* RCIN is C RCIN R RCIN = A close value is C RCIN = 12nF. The las sep in he design procedure is o verify he proper discharge of C RCIN wih he seleced values for R RCIN and C RCIN The discharge ime is shor enough o ensure a safe shu down of he power ransisor and a lach of he ITRIP even. Neverheless, a pracical verificaion by measuremens in he sysem is required. 2.4 Limiaions of he proposed soluion 1) I RCIN = ( 50% 20% 1) 2.8 µa = 4.2 µa (6) V pu I charge,rrcin = 8.2 V 4.2 µa = 1.95 MΩ (7) = FLTCLR,arge 10 ms C RCIN = 10 nf = 11.8 nf (8) RRCIN,CRCIN 8.5 ms discharge = R on,rcin C RCIN ln V h,rcin V pu = 40 Ω 12 nf ln 3.2 V 8.2 V = µs (9) The limiaion of his approach is he discharge condiion according o equaion (1). The concep of he proposed soluion is based on he assumpion ha he discharge of capacior C RCIN is faser han he minimum oal shu down delay ime. This ime includes he IC s minimum shudown propagaion delay ITRIP,min and he power ransisor s minimum urn-off propagaion delay (off),min. This is difficul o achieve for power ransisors wih a very small curren raing. Furher limiaions are especially oher componen olerances, such as he capaciance C RCIN, he emperaure influence on resisance R RCIN or he zener volage olerances. Applicaion Noe AN <Revision 2>, < >

7 Overcome he high rigger level of he ITRIP funcion 3 Overcome he high rigger level of he ITRIP funcion This secion describes how he high rigger level of he overcurren shu down funcion can be adaped owards lower levels. 3.1 Applicaion problem The shun, which is locaed in he emier pah of a low side IGBT, generaes a volage according o is bias poin. This volage is filered by means of a / C F combinaion according o Figure 5. COM 6ED family ITRIP 2nd generaion V IT,HYS = 70mV INPUT NOISE To C F V IT,TH+ = FILTER RS-lach R v ITRIP SH V Z =10.5V 0.445V Comp. Figure 5 ITRIP funcion The ITRIP rigger level of V IT,h+ = V is fixed for he 6EDL family 2 nd generaion. The adjusmen of he riggering curren level is done by adjusing he shun value, so ha he shun s volage will rigger he ITRIP even. However, applicaions wih high load currens will dissipae a considerable power in he shun. For example, a curren rigger level of 50 A would dissipae a power of 50 A V = W. Therefore, he curren rigger level should resul in a low shun volage in he area of 100 mv o 200 mv in order o reduce he power dissipaed in he shun. 3.2 Applicaion soluion The applicaion soluion is implemened by an addiional volage drop over he filer resisor. The volage drop is generaed by a curren added by a pull up-resisor R pu according o Figure 6. +5V COM R pu 6ED family ITRIP 2nd generaion V IT,HYS = 70mV INPUT NOISE To C F V IT,TH+ = FILTER RS-lach R v ITRIP SH V Z =10.5V 0.445V Comp. Figure 6 ITRIP funcion wih pre-bias circui The required volage drop of he resisor is calculaed wih This resuls in a required pull-up curren of V IT,h = V RF + V SH,max V RF = V IT,h V SH,max (10) I RF = V RF (11) Applicaion Noe AN <Revision 2>, < >

8 Overcome he high rigger level of he ITRIP funcion Now he pull-up resisor value which provides he curren I RF can be calculaed R pu = V pu V IT,h I RF (12) 3.3 Applicaion example The example in his documen is based on hese condiions and assumpions: The riggering curren of an ITRIP even should resul in a shun volage of 200 mv The pull-up volage is 5 V = 1 kw ( R SH ) The execuion of equaions (10) - (12) is The pull-up curren will be V RF = V IT,h V SH,max = V 0.2 V = V (13) I RF = V RF Now he pull-up resisor value which provides he curren I RF can be calculaed R pu = V pu V IT,h I RF A selecion of R pu = 18 kw is possible. The design verificaion sep execues he reworked equaions (12) - (10) using he seleced componen values. I RF = V pu V IT,h R pu = V 1 kω This resuls in a volage drop a he resisor of = 5 V V ma = 5 V V 18 kω = ma (14) 18.6 kω (15) = ma (16) V RF = I RF = ma 1 kω = V (17) The ypical error is smaller han 5% and herefore accepable wih respec o he overall olerance of he ITRIP funcion. 3.4 Limiaions of he proposed soluion The mos dominan limiaion is he overall olerance of he ITRIP funcion. I is of course possible o reduce he riggering shun volage of his funcion. However, he absolue olerance of ± 65 mv remains. A very precise overcurren shu down funcion can be achieved wih his proposal. Neverheless, he secure shu down of shor circui evens is no jeopardized. Addiionally, he ITRIP hyseresis mus be considered, so ha he larges usable volage drop over he resisor is V IT,h+,min V IT,hys,yp = 380 mv 70mV = 310 mv. Therefore, he resuling smalles shun volage is 65 mv + 70 mv = 135 mv. An addiional margin of approximaely 50 mv is recommended in order o ensure a proper power up. Applicaion Noe AN <Revision 2>, < >

9 Overcome he high rigger level of he ITRIP funcion References [1] Infineon Technologies: 6EDL family 2 nd generaion; Daashee; Infineon Technologies, Neubiberg, Germany. [2] Infineon Technologies: 6EDL family 2 nd generaion Technical descripion; Applicaion Noe AN- EICEDRIVER-6EDL04-1; Infineon Technologies, Neubiberg, Germany. [3] Infineon Technologies: IKD06N60RF; Daashee; Infineon Technologies, Neubiberg, Germany. Revision Hisory Major changes since he las revision Page or Reference Descripion of change Applicaion Noe AN <Revision 2>, < >

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