SEMICONDUCTOR APPLICATION NOTE


 Jayson King
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1 SEMICONDUCTOR APPLICATION NOTE Order his documen by AN1542/D Prepared by: C. S. Mier Moorola Inc. Inpu filer design has been an inegral par of power supply designs. Wih he adven of inpu filers, he designer mus ake ino consideraion how o conrol he high inrush curren due o rapid rise of volage during he iniial applicaion of power o he power supply. Depending on he inpu bus volage level and he oupu power required by he load, he supply designer mus also design he inducor (if used) o suppor he DC curren wihou sauraing he core. The inducor and capacior is designed o mee EMI requiremens. Limiing iniial inrush curren wih inducor can become very large in size and weigh, and in mos cases size and weigh is a crucial requiremen o he design. In his secion, a review of various acive and passive mehods of inrush limiing echniques are presened. I is shown ha a new and innovaive mehod can be applied using a single MOSFET and a minimal number of componens in many of he circuis requiring dv/ conrol in order o limi he high curren spikes. Is design mehods and simple ye effecive equaions are also presened. A variey of applicaions of his dv/ conrol circui ino oher areas are proposed. The simpliciy and he advanage of his echnique, as opposed o oher echniques, is shown given is effeciveness in differen applicaions requiring dv/ conrol. The new inrush limiing is beneficial because dv/ conrol reduces he EMI due o curren and volage spikes, and he lifeime of capaciors and he semiconducor devices surrounding he circuiry is increased. This echnique will also increase he reliabiliy of he devices and he capaciors. And because of is minimal pars coun, he design is very cos effecive. INTRODUCTION In power supply designs, he inpu filer design is an inegral par of he design. In mos designs inpu filer designs incorporae boh inducor and capaciors. The inducor and capaciors need o behave in such way as o provide EMI reducion and provide supply hold up requiremen in case of shor duraion line dropou. This requiremen along wih deraing of he capaciors for emperaure variaions resuls in having o use large filer capaciors. Wih innovaions in echnology, he process for manufacuring of capaciors allows for very low equivalen series resisance (ESR), and hus hey behave like nearly perfec shor circuis during iniial power applicaion o he power supply [1]. The iniial power applied o he power supply posses a very high dv/. This high dv/ ineracing wih he filer capaciors will inroduce shor duraion of high peak curren which can exceed far beyond he device raings (semiconducor devices, fuses, circui breakers), and can seriously damage or desroy he semiconducor devices, burn ou he fuses or false rigger he circui breakers. The high rae of rise of he volage and fas rise of he curren may acivae oher circuiry ha are dv/ and di/ sensiive. This high dv/ and di/ inroduces unwaned EMI noise. I is clear ha a new mehodology of conrolling dv/ wihou affecing he inducor size and power supply efficiency needed o be found. VARIOUS INRUSH LIMITING TECHNIQUES Tradiionally, mos of he inrush curren limiing is done by using a large oversized inducor, or resisors in series wih he capaciors. These echniques do no opimally uilize he surface area, weigh and power dissipaion. In applicaions where large DC curren is required a he inpu of he power supply, he inducor no only has o be designed for low EMI, bu i needs o be designed o mee DC curren capabiliy wihou degrading he inducance value. Reducion in inducance will mean ha he EMI noise aenuaion capabiliy is reduced. Therefore, he design of inducance becomes very large because wih increase in operaing curren, he core becomes larger. If a series resisor is used, unnecessary power is los because of I2xR. This in urn degrades he power supply efficiency. In order o overcome he power dissipaion of he series resisor, many designers incorporae a parallel swich wih a resisor (semiconducor devices or relays). Depending on he operaing curren, he relay can become excessively large and heavy. In addiion, conrol circui mus be implemened in order o conrol he urn on and urn off of he relay. In he cases where semiconducors are used, such as an SCR, he device can become very bulky and dissipaive. This applicaion also requires unique conrol circuiry in order conrol he SCR urn on and urn off. Anoher mehod of inrush curren limiing is done using an NTC hermisor. This device has a negaive emperaure coefficien and is resisance decreases as curren is passed hrough he device (curren flow increases he emperaure of he device and decreases he resisance) [2]. The drawback of his device is ha i requires a cool off ime afer he power is removed in order o rese o high resisive mode. Depending on he power raing of hese devices, is physical size becomes significan. The cool off ime can be overcome by using an acive device along wih he NTC device. Bu his defeas he purpose of using he NTC device in firs place; ha is, he simpliciy of applicaion and minimal pars coun. MOTOROLA Moorola, Inc
2 Vdc L C Figure 1. Inducive DC DC POWER CONVERTER MOSFET Swiching Characerisics MOSFETs are charge conrolled devices and can be represened wih he simplified equivalen circui shown in Figure 4. The gae source capaciance (Cgs) is largely dependen on gae oxide and source meallizaion capaciance and can be measured and considered consan. Gae drain capaciance (Cgd) consiss of he gae drain overlap oxide capaciance and gae drain overlap depleion capaciance. This capaciance is nonlinear due o is volage dependency. Drain source capaciance is he depleion capaciance of he drain source juncion. The following expressions can be obained from he circui shown in Figure 4. D R ICgd Idrain D1 D2 AC INPUT D4 D3 SCR CONTROL CIRCUIT + DC DC C POWER CONVERTER G IG Cgd Cgs Cds Figure 2. Passive and Acive Figure 4. Equivalen Circui for MOSFET S NTC AC INPUT D1 D4 D2 D3 NTC + DC DC C POWER CONVERTER Ciss = Cgs + Cgd; Cds shored (1) Crss = Cgd, (2) Cgs Cgd Coss = Cds + ; Cgs + Cgs shored Cgd (3) Cds + Cgd Figure 3. NTC Thermisor INTRODUCTION TO ACTIVE CURRENT LIMITER In low o medium power levels which require few hundred vols of blocking capabiliy, MOSFETs are an ideal devices because hey posses following characerisics: 1) fas swiching ime due o majoriy carrier devices, 3) lower swiching loss due o fas rise and fall imes, 2) simple gae drive, 3) and low RDS(on) which helps o increase he efficiency by decreasing he volage drop across he device during seady sae conducion. Because he acive curren limiing is done by using MOSFET devices, i is essenial ha one comprehend he swiching characerisics of his devices. By undersanding he swiching characerisics, he design engineer will be beer equipped o use he proposed circui wihou any ambiguiy. The expressions shown in equaions 1 hrough 3 are parameers ha are available from he MOSFET daa shees and curves provided herein. Capaciance Ciss is equivalen inpu capaciance, Crss is he reverse ransfer capaciance, and Coss is he equivalen oupu capaciance. How fas he capaciance is charged and discharged deermines how fas he device will urn on or urn off (here he load effec on swiching of he device is no considered). The mos effecive way of obaining and conrolling he swiching mechanism of he MOSFET is by using he gae charge ransfer curves as provided by he vendors. 2 MOTOROLA
3 Figure 5 shows he urn on gae charge ransfer curve. This curve conains all he necessary informaion for conrolling he urn on swiching of he device. Region 1 is a pre hreshold region and he consan curren is used o charge he inpu capaciance Ciss. During his period, we can ignore he gae drain capaciance because i is much smaller han he gae source capaciance and VGS rises o device hreshold volage Vh a a linear slope. When VGS has reached he Vh, he drain curren rises o is seady sae drain curren during he region. In region 2, he drain source volage sars is ransiion and he gae charge ransfer curve sars o level off. The slope of he drain source volage is much higher in region 2 because he gae drain capaciance Cgd is sill relaively small and his small capaciance can be discharged a a faser rae wih he given gae curren. As he volage across he drain gae is reduced even more, he dramaic increase in Cgd is observed, and i is his large capaciance which will dominae he inpu capaciance, and all of he gae curren is used o discharge Cgd. During his fla level (region 3), VGS remains consan, VDS decreases o is sauraion volage, and Vsa, and he VGS will again rise o is applied gae volage value. Furher increase in VGS has no effec on he drain source volage and drain curren. han he inernal Cgd, we can rewrie equaions 1 hrough 3 (see Figure 6). G IG ICgd Cgd Cgs D S Cds Figure 6. Revised MOSFET Circui wih Exernal Capacior Given he condiion: >> Cgd Idrain Ciss = Cgs + Cgd + + Cgs: Cds shored (4) V VGS Crss = Cgd + (5) Coss = Cds + Cgd + ; (6) VDS 90% VGS2 VGS1 10% Figure 5. Gae Charge Transfer Curve The exernal capaciance acs as an inegraor and is used o accuraely deermine he swiching characerisics of he MOSFET. Is simple expressions allow us o disregard much of he nonlinear capaciive effecs of Cgd because he capaciance,, along wih he gae drive dominaes he drain source volage ransiion. The abiliy o conrol he consan linear slope of he drain volage ransiion allows accurae conrol of he inrush curren o he capaciive load. This is possible because he curren flowing hrough he capacior is dependen upon he ransiion of he Volage: ic C dv. (7) In observing he gae ransfer curve, i is seen ha he VDS ransiion is deermined during region 2 and region 3 of he curve. If he drain source volage ransiion is conained in region 3, i is possible o fix and conrol he ime rae of change of he drain source volage, dvds/, very accuraely. The abiliy for conrol of region 3 will allow complee conrol of he dvds/ independen of load condiion. I is his abiliy o conrol dvds/ which will allow conrol of he inrush curren o he capaciive load or resisive load. Proposed MOSFET Swich In order o insure ha he volage ransiion is linear hroughou region 3, an exernal capacior can be added o he gae drain connecion,. If his capaciance is much larger Derivaion of he Design Equaions for dv/ Conrol Circui Figure 7 is a circui used o conrol he dv/ of he MOSFET during is swiching cycle. is a series gae resisor (which is large in value), and D is a small resisor added in series wih o damp ou any unwaned high frequency oscillaions (his resisor mus be much smaller in value han : >>D. The large value of conrols he charge rae of he ). The conrol of he dv/ is dependen upon he load ype and is a funcion of gae volage,,, exernal feedback capaciance, and drain curren of he device. The diode, Dg, is placed in parallel wih he o provide faser urn off process, and can be aken ou if slow urn off is of no concern. MOTOROLA 3
4 LOAD ICgd L C R Dg D GATE DRIVE IG Cgs NMOS Figure 7. dv/ Conrol Circui Figure 8 is a swiching characerisic of dv/ conrol circui of Figure 7, and his curve will be analyzed o derive all of he design equaions for he dv/ circui. Turn on delay is defined as he ime required o charge he gae source o hreshold volage, Vh. The ime delay can be found by using he following equaion: v d = (Cgs + ) ln 1 V h, (9) Vh VDS Vpl Idrain VGS Figure 8. Gae Source Charge Characerisic Region 1 During his period, he gae volage is charging he equivalen inpu capaciance which is dominaed by he feedback capaciance,, expressed in equaion 4. This consan capaciance gives consan linear slope, and he gae source volage will rise exponenially: VGS = [1 e [/((Cgs+)] ] (8) Region 2 Beyond he urn on delay, region 2, he drain curren sars o conduc. The ime rae of change of drain curren is expressed as: didrain = gfm dvgs (10) Where dvgs/ is a represenaion of he slope for regions 1 and 2, and gfm is he ransconducance o suppor he drain curren Idrain. During his ime he drain volage is nearly consan. Region 3 In region 3, he ransiion of he drain source volage occurs from is blocking volage o is sauraion volage once he drain curren has reached is maximum load curren, and he gae source volage remains a plaeau volage Vpl. Noe he difference beween Figure 6 and Figure 7. In Figure 7, he ransiion of drain source volage exends linearly unil he end of region 3. The swiching is compleed when he drain source volage VDS has swiched o 10%. Since he drain curren is consan during his region, he gae source volage (he plaeau volage, Vpl) mus be: Iinrush Vpl = Vh + gfm(max) (11) 4 MOTOROLA
5 This plaeau volage can be found by using a ransfer curve provided by he vendors (see Figure 9). ID, DRAIN CURRENT (AMPS) VDS = 10 V TJ = 55 C 100 C VGS, GATE TO SOURCE VOLTAGE (VOLTS) Figure 9. MOSFET Transfer Characerisics 25 C The consan Vpl allows he inpu curren o flow hrough he feedback capaciance,, and is curren is expressed as: ( Vpl) Ig =. (12) Bu since he gae curren is equal o he curren flowing hrough feedback capaciance,, we can rewrie he above equaion as a funcion of, VDS, Vpl, and ime, : Given: Igd Ig, dvds Igd. Thus he rae of change of gae drain volage is: dvgd = Ig = ( Vpl). (13) (14) The ime rae of change of drain source volage is equal o he ime rae of change in gae drain volage during he region 3. I is expressed as: dvds = (V GG Vpl). (15) Region 4 In region 4, he VDS has reached is Vsa and VGS coninues o increase o is gae volage,. dv/ Design Seps The following seps are given in order o simplify some of he equaions, and o simplify design procedures. 1. Use equaion 7 o find he ime required o mee he inrush requiremen: = Cfiler.. Iinrush (16) 2. Find he gae source plaeau volage, Vpl, required o supply he load curren (equaion 11). Use he device ransfer curve o find he plaeau volage if he daa is available. Iinrush Vpl = Vh +. gfm(max) (17) 3. Choose based on following condiion: >> Cgs + Cgd (he values for Cgs and Cgd is obained using he daa shee curves). 4. Find he gae curren required using equaion 13 (he feedback capaciance is chosen based on availabiliy): dvds Igd. 5. Use equaion 12 o find he series gae resisance: ( Vpl) =. Igd 6. Choose D: >> D. (18) (19) dv/ Design Example. Figure 10 is a es circui which have been incorporaed o es he effeciveness of he circui. Following parameers were used: Cgs = 2000 pf = 28 Vdc Cfiler = 200 µf Iinrush = 2 Apk = 12 V Vh = 2.7 V gfm(max) = 2.5 S Cload ICgd Dg SWITCH Cgd NMOS IG Figure 10. dv/ Conrol Tes Circui MOTOROLA 5
6 Sep 1 Using he expression i = C(dv/), he ransiion ime for VDS is found: = Cfiler. Iinrush = 200 µf 28 2 = 2.8 ms (20) Sep 2 During he VDS ransiion, VGS is consan and equaion 11 is used o find he Vpl for desired peak drain curren (use he ranfer curve if available). Vpl = Vh + Iload gfm(max) = = 3.5 V. (21) Sep 3 Saisfying he condiion >>Cgs+Cgd, 0.1 µf was arbirarily chosen. We can eiher choose iniial value of or, and design for he unknown. Bu in mos cases, differen values of resisor is easier o obain han he capaciors. So for his design example, was chosen. Sep 4 Use equaion 14 o find required gae curren: Igd dvds 0.1 µf ms 1 ma. (22) Sep 5 Using he calculaed values from 21 and 22, series gae resisor is calculaed: = (V GG VGS) Igd = (12 3.5) 1 ma 8.5 kω. (23) Sep 6 The damping resisor can be chosen arbirarily if he following condiion is me: >> D, Le D = 100 Ω. di/ Design In some cases he iniial rae of rise of he drain curren mus be limied o some fixed rae. The curren slope limiing reduces ransiens associaed wih L(di/) due o sray inducances. This curren slope limiing reduces he problem of loading of he line which can cause a emporary line dropou [3]. We can deermine from he Figure 11 ha ime for VGS o reach a volage level given by equaion 11 mus be greaer han he sum of delay ime, d, and he ime required for drain curren o reach seady sae value: Vgs > d + di. (24) Where Vgs is he ime required for VGS o reach a value ha will suppor he inrush curren obained by equaion 17, and Iinrush is he maximum inrush curren flowing hrough he MOSFET. VOLTAGE d Vgs di Vpl Figure 11. Expanded View of Gae Source Volage VGS TIME The rae of rise ime of he drain curren of he device is direcly proporional o he rae of rise of he gae source volage (see equaion 10): didrain dv GS (25) The rae of change of drain curren is a design requiremen. As a resul, we can find he minimum ime required for gae source volage o reach he value o suppor he iniial inrush curren: Vpl Vgs(min) =. (26) (diinrush / ) Using he minimum ime required, he following mus be saisfied: (Cgs + ) ln Vgs(min) 1 V pl (27) If he above expression is no saisfied, hen one of he parameers ( or ) mus be changed o saisfy he equaion. di/ Design Example. For he same circui used for dv/ conrol, he following curren requiremen mus be me: didrain Sep 1 The minimum ime required is: = 2A 100 µs. 3.5 Vgs(min) = = 175 µs. (2 A/100 µs). (28) (29) 6 MOTOROLA
7 Sep 2 Once oal ime required is calculaed, he ime consan can be checked (he effec will be discarded): (30) (Cgs + ) = 8.5K (2000 pf µf) = 867 µs. and, Thus ln Vgs(min) 1 V pl (Cgs + ) ln = ln Vgs(min) 1 V pl 175 µs = 507 µs. (31) = 867 µs 507 µs. (32) The condiion is saisfied and nohing needs o be changed. If equaion 32 was no saisfied, a differen value of (or ) can be chosen. CONCLUSION I is shown in his secion ha by using a low RDS(on) MOSFET in curren limiing, he shorcomings due o passive mehods can be overcome. Using an MOSFET device in an acive dv/ and di/ conrol is useful due o he simple gae drive requiremens and low RDS(on). Wih jus a single MOSFET and is corresponding componens, dv/ and di/ ransiion can be accuraely conrolled. This conrol circui resuls in precise conrol of inrush curren magniude, and reduces much of high frequency noise associaed wih high volage and curren ransiions. No only is he circui precise, bu i also reduces weigh and surface area as opposed o bulky inducors. The simple and ye effecive equaions have been derived for dv/ and di/ conrol circui. These simple equaions wih appropriae componens can overcome even some of he mos sringen inrush curren limiing requiremens wihou sacrificing weigh and area. The following are he design objecives which have been discussed: 1. Add a feedback capaciance o negae nonlinear volage dependen capacior Cgd. 2. The following requiremen mus be me: >>Cgs+Cgd (maximum Cgd can be obained from he vendor daa). 3. Linearize rae of change of drain source volage during all of he acive region (region 3). 4. Conrol dvds/ by conrolling he charge rae of. 5. Fix he charge rae by conrolling he charging curren. 6. Gae curren IG, is fixed during acive region by choosing correc. MOTOROLA 7
8 APPLICATIONS USING DV/DT CONTROL CIRCUIT INTRODUCTION The acive dv/ circui is applicable o many applicaions which require slow ramp up of volage across he load or curren hrough he load. Deailed analysis was done in previous secion of he paper which showed all of he required design equaions. Using his same equaions, and wih sligh modificaions, dv/ circui can be implemened o numerous applicaions. In his secion some examples will be shown and discussed where i is appropriae. V VGS Vpl Series Pass Swich There are requiremens where he power o he load mus be swiched on a a conrolled rae eiher 1) due o inrush curren requiremen o capaciive load or 2) due o power source ype (baeries). Using a MOSFET o swich on he power o he load allows he flexibiliy of accuraely conrolling he dv/ and di/ o he load. Using a conrolled ramp up of power o he load also relaxes some of he load ransien requiremens for primary power source (DC DC SMPS). The following examples are circuis used for swiching power o he load. The examples are given o show how he differen device ypes can be implemened in a swiching load applicaion using he dv/ conceps discussed previously. The same design seps can be followed as in previous secions. Bu for simpliciy, all he seps will be rewrien for he convenience of he reader. PMOS Applicaion Given: oupu volage ransiion ime, Given: oupu volage, Vou Given: gae volage, Given: gae drain capaciance, Given: gae source plaeau volage, Vpl Vou = Figure 2. PMOS Swiching Transiions NMOS Applicaion When NMOS is used o swich he power o he load, he gae volage of he device is consanly increasing nonlinearly due o he oupu volage level shifing he gae source volage, V GS (see Figure 4). Idrain D I D NMOS S G Vou LOAD 1. Choose >> Cgs + Cgd 2. Igd dv DS = Vou 3. = V DD Vpl or (2) Igd = V DD Vh : if very low oupu curren (in ma). (3) Igd (1) VOLTAGE IG Figure 3. NMOS Load Swich Choose D <<. PMOS S G D I D Vou LOAD 0 0 ACTUAL CURVE Vpl VT LINEARIZED VG VGS Vou IG Figure 1. dv/ Conrol Circui Used As Load Swich 0 Figure 4. Volage Transiions of NMOS Swich TIME 8 MOTOROLA
9 The gae volage is changing a a rae: VG = (1 e (/D)) (4) Noe ha gae volage has o be greaer han he inpu dc volage; > dd. Taking his assumpion we can han linearize he gae volage curve and he following design requiremens be implemened: 1. Choose >> Cgd + Cgs 2. Find he gae volage a which he oupu will have ramped up o is inpu volage: VT = Vpl + Vou (5) 3. Find he oal ime required for gae volage o reach VT: Vou =, (6) VT INRUSH CURRENT LIMITER FOR DC DC CONVERTERS Figures 5a and 5b shows he dv/ circui used as a inrush curren limier in a DC DC power converer (The operaion of he circui is no discussed in his secion, bu is presened in he following secion). In Figure 5a, he MOSFET is placed in he reurn pah of he power supply. This will cause he SMPS pah o rise o he value, and hen i is brough down o ground poenial a a fixed rae by he dv/ conrol circui. This configuraion is beneficial where he RDS(on) of he MOSFET does no inroduce an addiional ESR o he filer capacior. Figure 5b shows he dv/ circui placed in series wih he inpu filer capacior. This configuraion is beneficial because he MOSFET can never be shored due o improper ground connecion, and he RDS(on) can ac as an damping resisor. and = VT Vou, (7) where,, is equal o ime needed for gae o charge up o VT. Cfiler DC DC SMPS 4. Calculae he series gae resisor using he ime, : =. ln 1 1 V T. (8) Rch D NMOS SMPS Choose D <<. Sample Calculaions: Given: = 5 V Vou = = 5 V = 12 V = 5 ms Vpl = = 0.1 µf (9) DC Vdc Cch Dg Figure 5a. MOSFET Placed a Reurn Pah L Dgs Cfiler DC DC SMPS 2. VT = Vpl + Vou = = 7.7 (10) 3. = VT Vou 7.7 = 5 ms = 7.7 ms (11) 5 Rch D NMOS SMPS 4. 1 = =. 7.7 ms ln 1 V 0.1 µf. T (12) DC Cch Dg Dgs ln = 75 kω Figure 5b. MOSFET Placed Series Wih Filer Capacior 5. Le D = 100 MOTOROLA 9
10 INRUSH CONTROLLER FOR DC LIGHT BULBS In order o prolong he lifeime of incandescen lamps, he inrush curren mus be conrolled (i can be any ligh emiing device). If many ligh bulbs are paralleled, he peak curren o he load mus be conrolled because i may exceed he fuse or circui breaker raing. By using he dv/ conrolled circui, he inrush curren can be conrolled accuraely. Iniially he ligh bulb has very low cold resisance, bu once he curren is conducing he filamen warms up and is resisance increases accordingly. The dv/ conrol circui is used so ha he volage across he lamp will increase very slowly, and his slow rise of he volage will allow he lamp o hea up before he full supply volage is across he lamp. CONCLUSION Rch D NMOS Acive dv/ conrol circui can be applied o numerous applicaions where volage and curren mus be conrolled a iniial urn on. I was shown in his secion ha he circui can be implemened in series swich o he load, conrol inpu filer inrush curren, and conrol inrush curren o he dc ligh bulbs. Using dv/ conrol circui is beneficial because i reduces he EMI and prolongs he lifeime of he elecronic componens in he circui. DC Cch Dg Dgs Figure 6. Inrush Limier for Incandescen Ligh Bulbs 10 MOTOROLA
11 AVOIDING FALSE TURN ON DUE TO STATIC DV/DT FOR MOSFET BASED ACTIVE INRUSH CURRENT LIMITER Figure 1 is a acive inrush curren limier incorporaed ino DC DC power converer. Iniially he NMOS swich is urned off unil he dc buss volage is applied. In many applicaions, he inpu volage is swiched. The rae of rise of he supply volage is a funcion of he swich speed and he parasiic componens wihin he circui. When is fully applied o he circui, he drain of he MOSFET will see all of he applied volage because of is high impedance during off sae. When high dv/ is applied o he drain of he MOSFET, he volage ransien can be fed back o he gae via drain gae feedback capaciance. If here is enough charge presen in he gae, he swich will urn on and he dv/ conrol will be los. The magniude of he gae source volage will depend upon he gae impedance of he device. DC Rch Cch Dg D Dgs Cfiler NMOS SMPS Figure 1. Inrush Curren Limier DC DC SMPS Figure 2 is a equivalen circui for MOSFET showing he inernal parasiic capaciance. In order o show how much impac he parasiic capaciance has during iniial volage applied o he drain of he device, consider he following example. Given: Cgd = 200 pf Cgs = 2000 pf = 100 V D We will assume he wors case (sep funcion). When is applied, he insananeous gae source volage will charge up o he following: VGS = Cgd Cgs + Cgd = = 9.1 V This volage is high enough o urn he device fully on and cause a large inrush curren o flow hrough he inpu filer capaciance. In Figure 1 he capaciance Cch is insered in order o keep he VGS a a level below he hreshold volage, and keep he device off during sep volage applicaion. Figure 3 shows he represenaion of he ime varying volage and curren waveforms for he circui shown in Figure 1. During he iniial applicaion of he volage, he gae volage will ry o ramp up because of high dv/ seen via he feedback capaciance, bu as soon as he gae source volage is high enough o urn he diode Dg on, i causes all of he charge o be ransferred o capaciance Cch. The volage across he charge capaciance Cch, is deermined by he volage division beween Cch and. This volage across he charge capaciance is expressed as: Vch =. (2) + Cch. The capaciance Cch mus be large enough in order o mainain he device in he off sae. The gae source volage will be: VGS = Vch + VDG, (3) where V DG is a juncion poenial of he diode Dg. Iniially, he curren flowing hrough he D, and is: io = V DD (4) D, and his curren decays exponenially a a rae: i = irgd = ioe /(D C gd ) (5) (1) ICgd Idrain VGS = Vch + VDG Cgd G Cds Vch = Cgd Cgd + Cch IG Cgs io e / (D Cgd) S Figure 2. MOSFET Equivalen Circui Figure 3. Sep Funcion MOTOROLA 11
12 During he sep volage applicaion, he volage across Cch is se a: Vch = Vhmin VDG = Vhmin 1. (6) This is o insure ha he MOSFET does no urn on during he iniial applicaion. In Figure 3, i is shown ha he iniial curren during he sep funcion is deermined by he D and. This curren han decays a some exponenial rae. In order for he VGS no o overshoo, he ime delay mus be provided by he RchCch ime consan such ha he gae source volage mus no rise o Vplaeau before he curren has decayed o near zero. If VGS has reached plaeau volage V pl, before he curren has decayed o zero, a overshoo will be observed a he gae and he device will urn on rapidly for a shor duraion and may cause excessive inrush curren o flow hrough he inpu filer capacior, Cfiler. Operaion of Charge Conrol Circui Figure 1 is a equivalen circui for inrush curren limier. When is applied, he charge capaciance mainains he VGS o a safe level so ha MOSFET does no urn on. The capaciance Cch is hen charged a a rae dependen on (Rch Cch) ime consan, and VGS charges a he same rae (a diode drop greaer) unil i reaches a volage o suppor he inrush curren. The drain volage decreases a a linear slope which is deermined by he ( ) ime consan. This slope hen deermines he maximum magniude of he inrush curren o he capaciors. Examples of he heoreical waveforms are shown in Figure 4. Design Equaions The oal decay ime required for he iniial curren is found by aking equaion 5 and solving for ime, : i delay = D abs ln, (7) io where i is he curren hrough he feedback capaciance a given ime. For his purpose, he desired curren level is se a 0.5% of iniial curren i o. The ime delay is han expressed as a funcion of feedback resisor D, and capaciance : delay 5.3 D (8) where he consan 5.3 is obained by: i abs ln = abs ln io The ime consan Rch Cch mus mee he following condiion: delay Rch Cch (10) (Vpl Vch VDG) abs ln 1 where, Vch is found by using equaion 6. The capaciance Cch is found using he following expression: and charge resisance, Rch is: Cch C gd ( Vch) Vch (9) (11) Rch 1 Cch. abs ln 1 delay (Vpl Vch VDG) (12) Vch VGS Vdrain Design Seps for Charge Conrol When designing for he Cch and D, following seps mus be done in order: 1. Find he volage Vch: Vch = Vhmin VDG = Vhmin 1 (13) 2. Using he calculaed Vch, find he capaciance Cch: Cch C gd ( Vch) Vch (14) 3. Find delay: delay 5.3 D (15) Find Rch: Idrain Rch 1 Cch. abs ln 1 delay (Vpl Vch VDG) (16) Figure 4. Swiching Waveforms 12 MOTOROLA
13 Design Example: 3. delay = 5.3 (0.01 µf 1K) = 53 µs Given: Vpl = 3.75 V Vhmin= 2 V = 50 V VDG = 1 V = 0.01 µf D = 1K Rch 0.49 µf. abs ln 53 µs ( ) K 1. Vch = 2 1 = 1 V 2. Cch = 0.01 µf (50 1) = 0.49 µf 1 CONCLUSION Acive inrush curren limiing can be accomplished wih a single MOSFET and few exernal passive componens. Bu in an environmen where high dv/ is observed, he designer mus make sure ha iniially he MOSFET remains off. In order o diver he charge a he gae of he device, a small capaciance Cch can be added. Using he appropriae equaions, correc values for Cch and Rch can be obained which will preven false urnon due o high dv/. In a noisy environmen, he charge capaciance will diver much of he noise away from he gae of he MOSFET. REFERENCES [1] Maingly, David. Increasing Reliabiliy of SMD Tanalum Capaciors In Low Impedance Applicaions, Technical Informaion, AVX (1994). [2] Clow, Dave, Loomba, Jee, Check, Ken. NTC Thermisors versus Acive Circuis for Inrush Curren Suppression, PCIM, (November 1993), pp [3] Humber, Donald L., Marin, Huber, Rainwaer, Sam L., Wienbreder, Ernes H. Acive Inrush Curren and Curren Slope Limiing, in Conference Rec HFPC., (1992), pp [4] Baliga, B. Jayan. Modern Power Devices, John Wiley & Sons, (1987), pp MOTOROLA 13
14 Moorola reserves he righ o make changes wihou furher noice o any producs herein. Moorola makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does Moorola assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion consequenial or incidenal damages. Typical parameers can and do vary in differen applicaions. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. Moorola does no convey any license under is paen righs nor he righs of ohers. Moorola producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he Moorola produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use Moorola producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold Moorola and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha Moorola was negligen regarding he design or manufacure of he par. Moorola and are regisered rademarks of Moorola, Inc. Moorola, Inc. is an Equal Opporuniy/Affirmaive Acion Employer. Lieraure Disribuion Ceners: USA/EUROPE: Moorola Lieraure Disribuion; P.O. Box 20912; Phoenix, Arizona JAPAN: Nippon Moorola Ld.; , NishiGoanda, Shinagawaku, Tokyo 141, Japan. ASIA PACIFIC: Moorola Semiconducors H.K. Ld.; Silicon Harbour Cener, No. 2 Dai King Sree, Tai Po Indusrial Esae, Tai Po, N.T., Hong Kong. 14 MOTOROLA AN1542/D
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