Astable multivibrator using the 555 IC.(10)

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1 Visi hp://elecronicsclub.cjb.ne for more resources THE 555 IC TIMER The 555 IC TIMER.(2) Monosable mulivibraor using he 555 IC imer...() Design Example 1 wih Mulisim 2001 ools and graphs..(8) Lile descripion on Conrol Volage and limis for exernal componens..(9) Asable mulivibraor using he 555 IC.(10) 1

2 THE 555 IC TIMER Block diagram represenaion of he 555 imer circui. The circui consiss of wo comparaors, an SR flip-flop and a ransisor Q1 ha operaes as a swich. One power supply is (Vcc) is required for operaion, wih he supply volage ypically 5V.A resisive volage divider, consising of he hree equal-valued resisors labeled R1, is conneced across Vcc and esablishes he reference (hreshold) volages for he wo comparaors. These are V TH = 2/ Vcc for comparaor 1 and V TL = 1/ Vcc for comparaor 2. Characerisics of Type S-R Flip-Flop S R Q Q 0 0 Q Q No change Rese Sae Se Sae 0 0? Unpredicable 2

3 Monosable Mulivibraor Using The 555 IC Figure above shows a monosable mulivibraor implemened using he 555 IC ogeher wih an exernal resisor R and an exernal capacior C. V rigger V TL Vc o Vcc V TH Vo T Vcc T

4 S R Q Q 0 0 Q Q No change Rese Sae Se Sae 0 0? Unpredicable 1-Iniial Sae :S=0 R=0 V Trigger > V TL Iniially, Because Vc=0V and V TH = 2/Vcc and so V TH > Vc he oupu of he comparaor 1 is 0V ha is R=0V(R=flip-flop inpu). Again because V TL =1/Vcc and V rigger > V TL he oupu of he comparaor 2 is 0V ha is S=0V(S=flip-flop inpu).when R & S is equal o 0V here will be no change a he oupus of he flip-flop.assuming he iniial oupu of flip-flop for Q=0V(ha is Vo) and so Q =1V(ha is ransisor bias volage). In he sable sae ha is Vo is equal o 0(Q=0) hus is Q oupu will be high, urning on ransisor Q1.Transisor Q1 will be sauraed, and hus Vc will be close o 0V.Curren coming from R will no charge C because curren choose he shor-circuied way ha is curren flows o he ground hru sauraed ransisor Q1.Look a he figure for sep Triggered signal applied, V rigger falls down below V TL. V Trigger < V TL S=1 R=0, Q=1 Q =0 To rigger he monosable mulivibraor, a pulse signal smaller han V TL is applied. As V rigger goes below V TL, he oupu of he comparaor 2 goes o he high level hus seing he flip-flop as S=1 R=0 for a shor-ime(i depends on pulse duraion). For S=1 and R=0 from he able he Q(Vo) will be high(vcc) and Q will be low(0v).q =0V will cause he ransisor Q1 o be off. Then curren will flow ino he capacior and i will charge he capacior. Explanaion will coninue in sep 4. Trigger signal makes S=1 for a shor ime, herefore capacior begins o charge - V rigger rises up above V TL S=0 R=0, Q=1 Q =0 (no change) The value of rigger signal below V TL lass for a shor ime. I rises up again above V TL.Then he oupu of he comparaor 2 will be again low(0v) and so S=0 and R=0 ha means flip-flop will no change is sae(q=1 Q =0) so capacior coninue o charge. Trigger signal reurns is sable sae ha makes S=0, capacior coninues o charge because S=0 and R=0 is no change sae oupus of flip-flop remains same 4- Capacior can charge up o V TH S=0 R=1, Q=0 Q =1 During charging when capacior volage (Vc) reaches V TH =2/Vcc oupu of he comparaor 1 changes is sae and he oupu of he comparaor 1 will be high.noe ha S is no equal o 1 because rigger signal rises up o is sable sae(above V TH ) quickly. S is equal o 1 only for a shor ime and his is enough for o sar he charging of he capacior. If he duraion of he rigger signal below V TL lass more han he duraion he capacior o be charged up o V TH hen S and R will be equal o 1 and ha will resul in unpredicable oupu of he flipflops. Now S=0 and R=1 ha means Q=0(Vo) and Q =1.Transisor will be sauraed again when Q =1 and so capacior will discharge quickly hru he sauraed ransisor(noe ha i will discharge very quickly because he resisance of he shor-circuied way is approximaely zero). 5- Capacior discharges quickly S=0 R=0, Q=0 Q =1(no change) Because he sauraed ransisor discharging he capacior, he oupu of he comparaor 1 will be again low(0v).now S=0 and R=0 ha means he oupu of he saes will remain same and Q(Vo) is equal o zero. This happenings will occur again unil a new rigger signal is applied. 4

5 Figure for STEP-1 Figure for STEP-2 C will no charge curren flows hru ransisor, shor-circui way. Capacior coninues o charge when rigger signal is applied. Trigger signal makes S=1 for a shor ime, herefore capacior begins o charge 5

6 Figure for STEP- S=1 makes Q=1 Q =0 and S reurns o 0 quickly.this will no affec he oupus of he flip-flop(no cahge sae).capacior coninues o charge. Figure for STEP-4 When capacior charges up o V TH, oupu of he comparaor 1 will be high and so R=1 S=0! Q=0 Q =1 This will cause o ransisor o be sauraed and capacior will discharge hru he ransisor y as i is indicaed. 6

7 Figure for STEP-5 Capacior will discharge quickly and V TH > V C so R=0 and S=0.This happenings will occur again if a new rigger pulse signal is applied. CALCULATION OF THE WIDTH OF THE OUTPUT PULSE : V rigger Vc Vo T V TL o Vcc V TH Vcc Vc can be expressed as: V C = Vcc(1 e / RC Subsiuing V C =V TH =2/Vcc a =T gives: 2 T / RC Vcc = Vcc(1 e T / RC 2 e = 1 T / RC 1 e = T = RC.ln T RC.1.1 ) ) T 7

8 EXAMPLE 1: Using a 1uF capacior C, find he value of R ha yields an oupu pulse of 1 second in he monosable circui of 555 IC. SOLUTION: T = RC.ln 1s =( R ). (1uF).ln R = 910.2KΩ Noe ha pulse widh of he V rigger is smaller han pulse widh of he oupu signal..v = V TH = (2/).Vcc (Vcc=5V) 8

9 Conrol Volage: By imposing a volage a conrol volage pin, he comparaor reference levels may be shifed eiher higher or lower han he nominal levels of one hird and wo hirds of he supply volage. Varying he volage a his poin will vary he iming. This feaure of he imer opens a muliude of applicaion possibiliies such as using he imer as a volage-conrolled oscillaor, pulse-widh modulaor, ec. For applicaions where he conrol i is srongly recommended ha a bypass capacior (0.01uF) be placed across he conrol volage pin and ground. This will increase he noise immuniy of he imer o high frequency rash which may monior he hreshold levels causing iming error. Limis for exernal componens: Manufacurers daashee will help us o deermine limi value of exernal componens.for example deermining R in monosable circui can be calculaed as: R Vcc V CAPACITOR max = I THRESHOLD can be obained from manufacurer s daashee. ITHRESHOLD For NE555 I THRESHOLD is 0.25uA V CAPACITOR is equal o 2/Vcc for monosable circui of 555 R MAX = (5V -.V)/0.25uA R MAX = 6.68MΩ Noe ha if using a large value of iming resisor, be cerain ha he capacior leakage is significanly lower han he charging curren available o minimize iming error. 9

10 Asable Mulivibraor Using he 555 IC Figure above shows an asable mulivibraor implemened using he 555 IC ogeher wih an exernal resisor R A, R B and an exernal capacior C. V C V TH o Vcc V TL Vo Vcc T H T L 10

11 1-Iniial Sae S=1 R=0! Q=1 Q =0 (C begins o charge) Iniially capacior is discharged or empy. A his ime V TH > V C causes oupu of he comparaor 1 o be 0 so R=0 and V TL > V C causes oupu of he comparaor 2 o be 1 so S=1. For S=1 and R=0, Q=1(high,Vcc) and Q =0(low,0V).Thus Vo is high and ransisor is OFF. Capacior C will charge up hrough he series combinaion of R A and R B, and he volage across i, Vc, will rise exponenially oward Vcc. 2- Vc V TL, comparaor 2! Low S=0 R=0! Q=1 Q =0 (no change, C is sill charing) As Vc crosses he level equal o V TL, he oupu of he comparaor 2 goes low.(vc V TL, comparaor 2! Low ). This however has no effec on he circui operaion because his will make he inpus of he flip-flop as S=0 and R=0 (no change sae) which means oupus of flip-flop will remain same. This sae coninues unil Vc reaches and begins o exceed he hreshold of comparaor 1, V TH. - Vc V TH, comparaor 1! High S=0 R=1! Q=0 Q =1 (C begins o discharge ) When Vc reaches and begins o exceed V TH, he oupu of he comparaor 1 goes high and reses he flip flop( S=0 R=1! Q=0 Q =1).Thus Vo goes low, Q goes high and so ransisor is urned ON. The sauraed ransisor causes a volage of approximaely 0V o appear a he common node of R A and R B. Thus C begins o discharge hru R B and he collecor of he ransisor. Noe ha R = 1(flip-flop inpu) for a very shor ime. 4- Vc V TH, comparaor 1! Low S=0 R=0! Q=0 Q =1 (no change, C coninues o discharge ) V C will drop again below V TH immediaely afer discharging process is sared.s=0 and R=0 will no affec he sysem(no change sae) The volage Vc decreases exponenially wih a ime consan R B.C oward 0V.This sae will coninue unil Vc reaches V TL. 5- Vc V TL, comparaor 2! High S=1 R=0! Q=1 Q =0 (C begins o charge ) When Vc reaches he hreshold of comparaor 2, V TL, he oupu of comparaor 2 goes high and hen S=1 R=0 causes Q=1 and Q=0.Thus oupu Vo goes high and Q goes low, urning off he ransisor. Capacior C begins o charge hrough he series equivalen of R A and R B, and is volage rises exponenially oward Vcc wih a ime consan (R A +R B ).C.This rise coninues unil Vc reaches V TH, a which ime he oupu of comparaor 1 goes high, reseing he flip-flop, and he cycle goes on. 11

12 Deerminig he Period T =T H + T L : For T H: From he general soluion for sep and naural responses : X() = X F + [ X( 0 ) X F ].e -(- 0) / τ Vc = Vcc + [ V TL Vcc] e /τ or ; V C = (Final Val Iniial Val) ( 1- e - /RC ) + shifing Vc = (b-a) ( 1- e - /RC ) + a /τ Vc = ( Vcc VTL )(1 e ) + V TL Noe ha : /τ Vc = ( Vcc VTL )(1 e ) + V TL is equal o Vc /τ = Vcc + [ VTL Vcc] e where τ =(R A + R B ).C V C o Vcc V TH V TL Vo Vcc T H T L Subsiuing =T H V C =V TH =2/Vcc and V TL =1/Vcc in he equaion 1 Vcc = ( Vcc Vcc)(1 e / τ 1 e = 2 2 / τ T H = (R A +R B ).(C).(ln2) T H = 0.69(C)(R A +R B ) 1 ) + Vcc where τ =(R A + R B ).C /τ Vc = ( Vcc VTL )(1 e ) + V TL For T L: X() = X F + [ X( 0 ) X F ].e -(- 0) / τ Vc = 0V + [ V TH 0] e Vc = V TH. e - / τ /τ where τ =R B.C 12

13 For =T L V C =V TL =1/Vcc and V TH =2/Vcc Vc = V TH. e - / τ 1/Vcc=2/Vcc. e - / τ where τ =R B.C T L = R B.C.ln2 T L = 0.69R B.C T = T H + T L T = 0.69(C)(R A +R B ) R B.C T = 0.69.C.(R A + 2R B ) Also he duy cycle of he oupu square wave can be found as: TH DuyCycle = T + T H L R = R A A + RB + 2R B Noe ha he duy cycle will always be greaer han 0.5(50%).I approaches o 0.5 if R A is seleced much smaller han R B. 1

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