Digital Systems Testing

Transcription

1 Digital Systems Testing Design for Test by Means of Scan Moslem Amiri, Václav Přenosil Embedded Systems Laboratory Faculty of Informatics, Masaryk University Brno, Czech Republic December, 2012

2 Introduction Most test generation schemes look at a CUT as a black box The only available nodes for testers to control are CUT s primary inputs, and to observe are its primary outputs This limited controllability and observability of CUT means complex test generation algorithms for circuits To overcome this difficulty in testing, digital circuits must become more testable by incorporation of design for test (DFT) techniques DFT techniques offer ways of making internal structure of a design more controllable and easier to observe Because such tasks are handled by designers, HDLs play an important role in facilitating insertion and evaluation of hardware structures that are put in a circuit for making it more testable Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

3 Making Circuits Testable A circuit is testable if tests can be generated for it efficiently, it can be tested with a high fault coverage, and the time it takes to test the manufactured part is reasonable Testability is a combination of controllability and observability A circuit becomes more testable by making it more controllable and more observable Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

4 Making Circuits Testable: Tradeoffs DFT techniques that make circuits more testable always introduce additional hardware that results in more pins, more delays, more power consumption, and a hardware overhead What we get instead is a better coverage and reduced test time In some cases, DFT techniques gain access to internal structures of a circuit that would otherwise be impossible to test Reducing the extra test hardware, its power consumption during test, the delay it introduces in design, and extra pins that are needed, are parameters a design engineer must optimize Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

5 Making Circuits Testable: Testing Sequential Circuits Generating a complete test for a sequential circuit is very complex Even if tests are generated, application of test requires many clock cycles to move a circuit into states that activate faults One of the most important contributions of DFT is making sequential circuits testable DFT techniques alter a sequential circuit model in such a way that combinational test techniques can be used for it DFT techniques define ways in which tests generated for a combinational model of a sequential circuit can be applied to actual sequential circuit Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

6 Making Circuits Testable: Testing Sequential Circuits Figure 1: Huffman model for test. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84 Huffman model is a useful model for sequential circuit testing A sequential circuit is modeled by a combinational circuit having feedback through delay elements In synchronous sequential circuits, delay elements are clocked flip-flops, and each feedback is a state variable Circuit primary inputs and outputs only apply to combinational part Synchronous or asynchronous set, reset, and other control inputs only apply to feedback flip-flops This model separates a CUT s registers from its combinational part

7 Making Circuits Testable: Testing Sequential Circuits Usefulness of Huffman model is in separation of registers and combinational part of a digital system This separation enables application of test methodologies to combinational part, and treating registers separately Since majority of a circuit s logic gates are contained in combinational part, testing this part, while considering register part inputs and outputs, covers majority of a circuit s faults Since flip-flops are treated as primitive building blocks in most technologies, testing a circuit for internal flip-flop faults is a secondary issue in most logic test systems Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

8 Making Circuits Testable: Testing Sequential Circuits Figure 2: Unfolded circuit model. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84 A circuit model that separates combinational and register parts, and puts focus of testing on combinational part is obtained by unfolding circuit model of Fig. 1 This is shown in Fig. 2 By unfolding a sequential circuit, its registers are separated and ignored Register outputs become pseudo primary inputs (PPI) for unfolded circuit, and register inputs become pseudo primary outputs (PPO) of this circuit Test results obtained from unfolded model are used by test equipment for testing actual circuit

9 Making Circuits Testable: Combinational Circuits Combinational circuits can also benefit from DFT techniques With an additional hardware inserted into a combinational circuit, it can be made to give a better coverage, reduce the number of test vectors required to test it, or achieve both at the same time DFT techniques alter a combinational circuit for better controllability and observability Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

10 Testability Insertion: Improving Observability Adding output pins improves observability Enables fault effects (that would otherwise not propagate to a primary output) to have a chance to show themselves through newly added output pins Results in fewer test vectors to test for faults, thus less test application time Lines with observability values below a certain threshold can be considered as candidates for becoming extra output pins State flip-flops outputs can also be made observable by pulling them out as primary outputs In Fig. 3, flip-flop outputs are pulled as primary outputs Starting in state V 1 V 0 = 10, while a = 1, SA0 fault shown can be detected in one clock cycle on new Out V 1 output Provisions for forcing this circuit into a certain state (e.g., V 1 V 0 = 10) are made in Fig. 3 0 or 1 insertion Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

11 Testability Insertion: Improving Observability a w SA0 0 or 1 Insertion 1D C1 Out V 1 V 1 V0 0 or 1 Insertion 1D C1 Out V 0 clk 1 Insertion 0 Insertion Figure 3: Basic testability techniques (observability, controllability). Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

12 Testability Insertion: Improving Observability In an RT-level design, appropriate places where extra output pins can be added are Control signals for flow of data through buses and logic units Logic and ALU control inputs Bus and multiplexer select inputs Multiplexer and decoder enable inputs Tri-state controls Register load input Count up and count down signals Shift-register mode control inputs Feedback lines Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

13 Testability Insertion: Improving Controllability Controllability parameters identify hard-to-reach places (low controllability lines) in a combinational circuit and add controllability there In sequential circuits Flip-flop inputs are good candidates for being directly controlled by circuit inputs In addition, controlling flip-flop reset and other control inputs help driving a sequential circuit into a given state In RT-level designs, direct control of control signals coming from a circuit s controller to its datapath enables testing of individual data operations independently Other places to add controllability Multiplexer and bus control inputs Tri-state control inputs ALU select inputs Counter and shift-register mode control signals Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

14 Testability Insertion: Improving Controllability a b Insert 0 Insert 1 Logic A Logic B Logic A Logic B 0 Inserting 1 Inserting c d Insert 0 Insert 1 Logic A Logic B Logic A 0 1 Logic B td NbarT 0 and 1 Inserting Normal and Test Data Figure 4: Several methods to add controllability. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

15 Testability Insertion: Improving Controllability Fig. 4 In (a), to drive a 0 into input of Logic B, Insert 0 must be set to 1 In combinational circuit testing, 0-insertion and 1-insertion structures are useful in places with low 0- and 1-controllability, respectively If hardware structures shown do not share pins with other test structures, 0- and 1-insertions require one primary input pin, while other two structures require two pins In all cases, timing delays are added between two logic parts Multiplexer has the largest delay Fig. 3 To force state V 1 V 0 = 10 into flip-flops, 1-insertion and 0-insertion structures should be used at inputs of flip-flop 1 and flip-flop 0, respectively Testing this circuit becomes easier by use of multiplexers at its flip-flop inputs Shown in Fig. 5 Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

16 Testability Insertion: Improving Controllability Figure 5: Put circuit into any desired state. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

17 Testability Insertion: Sharing Observability Pins When using observability points, to reduce cost of external pins, a multiplexer can be used An n-to-1 multiplexer can be used to multiplex n test points into one output pin Requires log 2 n input pins for multiplexer select inputs Multiplexing observation points prevents simultaneous observation of multiple observation points, thus increases test time In addition, multiplexer adds extra hardware and delay overhead n Points To Observe log n 2 Figure 6: Multiplexing observability points. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

18 Testability Insertion: Sharing Observability Pins Hardware shown in Fig. 6 can be repeated if multiple activation of several observation points are required For observing parallel buses, same bit positions of several buses can be grouped, and the hardware shown in Fig. 6 can be used for each group In this case, select inputs can still be shared, but actual output data pin must be repeated for each group Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

19 Testability Insertion: Sharing Control Pins To reduce pins required for controlling n internal lines of a circuit, a 1-to-n demultiplexer is used A demultiplexer is a decoder with an enable input Logic structure in Fig. 7 is for a 1-to-4 demultiplexer (2-to-4 decoder) S 1 S 0 En or Data y 0 n Points To Control y 1 y 2 S 2 S 1 S 0 y 3 Decoder / Demultiplexer Figure 7: Demultiplexer/decoder, reduce pins for control. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

20 Testability Insertion: Sharing Control Pins Figure 8: Sharing 0-insertion hardware. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

21 Testability Insertion: Sharing Control Pins Figure 9: Sharing test data insertion hardware. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

22 Testability Insertion: Sharing Control Pins Demultiplexing control points prevents simultaneous assignment of values to control points that share pins Therefore, simultaneous assignment of test data to bits of parallel buses is not possible unless hardware of Fig. 9 is repeated for each bus bit that needs to be controlled Figure 10: Simultaneous control of bits of buses. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

23 Testability Insertion: Reducing Select Inputs Figure 11: Selection input counter. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84 Although multiplexing observation points (Fig. 6) and demultiplexing control points (Fig. 7) significantly reduce test pin counts, for a large number of test points, we still have many pins for select inputs We can resolve this problem by adding a counter to CUT Counter is used for selection inputs For controlling or observing a line, counter counts up, and when it reaches the number of the test point, other test signals are issued Test time will be longer

24 Testability Insertion: Simultaneous Control of Test Points None of techniques discussed above allowed simultaneous activation of control or observe points Unless separate test pins were used and hardware structures were repeated (e.g., Fig. 10) To allow simultaneous control for several test points and still keeping the number of pins low, a shift-register can be used To take test data serially, and apply all bits in parallel in test mode Fig. 12 In normal mode, NbarT = 0 While in normal mode, test data can be shifted into shift-register without affecting normal operation Because test data shifting takes several clock cycles, we overlap normal operation with shifting test data into shift-register When test data are completely shifted in, CUT is put in test mode (NbarT = 1), which allows test data from shift-register to be used for input of logic blocks Serial shifting of test data is a time-consuming process One way to improve this is by use of a faster clock for test clock Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

25 Testability Insertion: Simultaneous Control of Test Points Figure 12: Shift-register for simultaneous control. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

26 Testability Insertion: Simultaneous Test Points Observation A shift-register can be used for simultaneous collection of values from several test points and shifting them out serially Fig. 13 In test mode, when response of CUT is ready at shift-register input, load input is enabled and shift-register is clocked Then load is deasserted, which puts shift-register in serial mode By applying n clocks in this mode, line values are shifted out Figure 13: Using a shift-register for simultaneous collection of line values. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

27 Testability Insertion: Isolated Serial Scan Isolated serial scan The two concepts of using a shift-register for controlling test points and one for observing them can be combined and the same shift-register can be used for both purposes Fig. 14 In normal mode, NbarT = 0 While in this mode, shift-register is put in serial mode and new test data are shifted in, while collected data from last testing to be observed (from YO3, YO2, YO1, YO0) are being shifted out At the end of shifting, CUT is put in test mode by asserting NbarT This applies test data in shift-register to inputs of CUT While CUT is propagating this test data, shift-register mode is changed to parallel loading Enough time is given for test data to propagate and show its effect on YO internal output lines At this time, shift-register is clocked just once to collect output This is followed by serial mode that shifts in a new test data while shifting out data that were just collected Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

28 Testability Insertion: Isolated Serial Scan Figure 14: Isolated serial scan. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

29 Testability Insertion: Isolated Serial Scan Fig. 15 Shows Verilog code of shift-register used in Fig. 14 TestMode = 0: does nothing TestMode = 1: right shifting TestMode = 2: parallel load TestMode = 3: resets shift-register Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84 Figure 15: Isolated serial scan shift-register.

30 Testability Insertion: Isolated Serial Scan Figure 16: Isolated serial scan virtual tester. Fig. 16 Shows pseudo code for equipment that connects to pins of CUT in Fig. 14 and tests it Since this code plays role of an ATE, it is referred to as a virtual tester Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

31 Full Scan The most common DFT technique is full scan Very similar in concept to isolated scan Problems with isolated scan Has an overhead of a shift-register Inclusion of this register still does not solve problem of test generation for sequential circuits We still have to treat CUT as a sequential circuit with a few extra test points for adding controllability and observability Full scan takes care of hardware overhead and sequentiality of CUT by incorporating required shift-register in CUT s state flip-flops Reduces hardware overhead CUT becomes virtually a combinational circuit Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

32 Full Scan: Full Scan Insertion Starting with Huffman model of a sequential circuit (Fig. 1) and unfolding it (Fig. 2), and applying testing to combinational part, covers all logic and register interconnection faults Full scan testing takes Huffman model of Fig. 1, and by inserting a shift-register in its register structures, makes a virtual model of the unfolded circuit of Fig. 2 Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

33 Full Scan: Full Scan Insertion Figure 17: Scan insertion. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

34 Full Scan: Full Scan Insertion Test procedure for testable Huffman model of Fig. 17 Only involves testing combinational part, and modified register is used as a mechanism for providing controllability of ps and observability of ns ps becomes pseudo primary inputs (PPI), and ns becomes pseudo primary outputs (PPO) of combinational part In normal mode (NbarT = 0), register loads ns to ps In test mode (NbarT = 1), test data (PPI) that is to be applied to ps is shifted into register When all data bits are shifted, first part of test data is ready at ps input (PPI) At this time, second part of test data is applied to circuit s primary inputs through external pins (PI) Combinational circuit takes the two-part test data (PI and PPI) and propagates it to its outputs Primary outputs (PO) are collected and stored We then put circuit in normal mode (NbarT = 0), and clocking circuit only once This causes ns part of output (PPO) to get clocked into register PPO is shifted out, so that together with PO forms complete output While this shifting is happening, we also shift in a new test data Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

35 Full Scan: Full Scan Insertion module FBRegister #(parameter size = 4)(input [size-1:0] ns, input STDI, Clock, NbarT, Reset, output STDO, output reg [size-1:0] ps); (posedge Clock) begin if (Reset == 1'b0) begin if (NbarT == 1'b0) ps <= ns; else ps <= {STDI, ps[size-1:1] }; //shift mode end else ps <= 0; end assign STDO = ps[0]; endmodule Figure 18: Testable Huffman model feedback register; ns = next state, ps = present state, STDI = serial test data in. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

36 Full Scan: Flip-flop Structures Verilog code of Fig. 18 assumes a simple flip-flop structure and a multiplexer for selection of normal and shift modes In addition to this structure, there are other structures that are more efficient in terms of timing and gate structures Latches cannot be used in feedback paths in sequential circuits unless complemented by other logic structures or other latches When clock is active, inputs of latches directly affect Q output Flip-flops can be used in sequential circuit feedback paths Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

37 Full Scan: Flip-flop Structures Figure 21: D-type flip-flop. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84 Figure 19: Basic latch. Figure 20: D latch. D 1D Q 1D Q Q D 1D Q Q C1 C1 C1 C

38 Full Scan: Flip-flop Structures Figure 22: Multiplexed scan element. module MuxedFF (input NbarT, Reset, DataIn, SerialIn, Clock, output reg OutFF); (negedge Clock) begin if (Reset) OutFF <= 1'b0; else OutFF <= ~NbarT? DataIn : SerialIn; end endmodule Figure 23: Multiplexed scan element Verilog code. Flip-flop of Fig. 22 Provides a close correspondence with Verilog description of Fig. 18 Can be used as a scan element for feedback register in Fig. 17 Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

39 Full Scan: Flip-flop Structures Figure 24: Scan register with multiplexed flip-flops. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

40 Full Scan: Flip-flop Structures Modeling multi-bit feedback registers We can use a Verilog code similar to scan code in Fig. 18 Appropriate for a behavioral description of a scan-inserted circuit Or, we can individually cascade flip-flops of Fig. 23 to form the right size register Useful in a netlist where low-level detailed simulations may be needed Flip-flop of Fig. 22 Is simple Has problem of multiplexer delay that adds to logic delay This structure increases the worst-case delay of circuit for which scan is inserted This reduces speed of normal system clock, and thus, a slower overall operation Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

41 Full Scan: Flip-flop Structures Dual clocking In Fig. 17, with each normal mode clock, ps output of feedback register must travel through entire combinational part to affect this part s ns output This involves a delay, only after which the register can be clocked again This delay is the worst-case delay of CUT, and its normal clock speed has to be slow enough to allow complete propagation of ps into ns through combinational part Such a delay does not apply when running circuit in test mode In this mode, we are only shifting data into shift-register, and the only logic is that between flip-flop bits (see Fig. 24) Therefore, test mode clocking can be faster than normal data clocking In larger circuits with many serial bits to shift-in, using a faster clock for test time gains a good saving in time Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

42 Full Scan: Flip-flop Structures DataIn DataClock SerialIn TestClock 1D C1 Q OutFF Figure 25: Scan flip-flop with dual clocking. module DualClockFF (input DataIn, DataClock, SerialIn, TestClock, output reg OutFF); wire Clock; assign Clock = DataClock TestClock; (negedge Clock) begin if (DataClock) OutFF <= DataIn; else if (TestClock) OutFF <= SerialIn; end endmodule Figure 26: Dual clock scan flip-flop Verilog code. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

43 Full Scan: Flip-flop Structures Fig. 25 AND-OR logic at flip-flop input selects DataIn when DataClock is 1 and selects SerialIn when TestClock is 1 While either clock is 1, proper data appear at flip-flop D-input, and after clock becomes 0, data at D are clocked into flip-flop Problems Hazard may occur in logic at flip-flop D-input Logic gates at inputs of circuit flip-flops increase the worst-case delay of circuit To reduce flip-flop D-input logic delay, clocking scheme of Fig. 27 can be used Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

44 Full Scan: Flip-flop Structures Figure 28: Two-port flip-flop timing. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84 Figure 27: Two-port three-clock flip-flop.

45 Full Scan: Flip-flop Structures Figs. 27 and 28 For loading DataIn into flip-flop, ClockA and ClockB are asserted alternatively, while ClockC remains at 0 For loading SerialIn, ClockC and ClockB are applied in alternative orders, and in this case ClockA is inactive When ClockA is asserted, while ClockB is 0, data on DataIn is latched into master latch and appears on M When ClockB is asserted, data on M is latched into flip-flop output Situation is similar when ClockA is inactive and ClockC toggles This flip-flop avoids multiplexer delay of previously mentioned flip-flops Clocking mechanism allows different clock speeds for normal and test modes This structure has overhead of having to handle three clock signals Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

46 Full Scan: Flip-flop Structures Figure 29: Two-port flip-flop symbol. Figure 30: Dual-port flip-flop Verilog code. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

47 Full Scan: Flip-flop Structures Figure 31: LSSD design. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

48 Full Scan: Flip-flop Structures LSSD (Level Sensitive Scan Design) (Fig. 31) Was first used by IBM in 1977 Overall operation is the same as that of Fig. 24 For normal operation, ClockA and ClockB are used In test mode, ClockC and ClockB become complementary clocks Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

49 Full Scan Design and Test This section shows flow of DFT from a problem specification to generating test and developing a test program The example that is used is Residue-5 circuit This is a sequential circuit, for testing of which DFT techniques are essential Residue-5 design should be taken through following steps (The last two steps will not be discussed) Design and design validation Synthesis and netlist generation Unfolding Combinational test generation Scan insertion Developing a virtual tester Test set verification Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

50 Full Scan Design and Test: Design and Design Validation Figure 32: residue5 partial Verilog code. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

51 Full Scan Design and Test: Design and Design Validation Residue-5 circuit is described in Fig. 32 Coding style is according to Huffman model of Fig. 1 Register part specifies a resetting mechanism, which means that this reset signal does not participate in combinational part of circuit Keeping reset and other flip-flop control signals away from combinational part is good for postmanufacturing testing The design described in an HDL must be validated A testbench for functional testing of design must be developed This topic has been covered before Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

52 Full Scan Design and Test: Synthesis & Netlist Generation Next step after design validation is synthesis Synthesized Verilog code of Fig. 32 is shown in Fig. 33 An FPGA-based synthesis program and a netlist converter are used here for synthesizing This netlist uses primitives that are compatible with PLI functions for fault collapsing, fault simulation, and test generation The netlist consists of basic gates with feedbacks through three flip-flops This is compatible with Huffman model of Fig. 1 Before going to next step of design, it is necessary to perform postsynthesis simulation of this netlist and make sure it is a correct translation of behavioral model of Fig. 32 Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

53 Full Scan Design and Test: Synthesis & Netlist Generation Figure 33: Postsynthesis residue5 netlist. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84 module residue5_net(clk, reset, in, out); input clk; input reset; input [1:0]in; output [2:0]out; wire wire_1, wire_2,... in_0_0, in_0_1,... out_0_0, out_0_1,... pin #(2) pin_0 ({in[0], in[1]}, {in_0, in_1}); pout #(3) pout_0 ({out_0_7, out_1_7, out_2_5}, {out[0], out[1], out[2]}); fanout_n #(8, 0, 0) FANOUT_3 (in_0, {in_0_0, in_0_1, in_0_2, in_0_3, in_0_4, in_0_5, in_0_6, in_0_7}); fanout_n #(7, 0, 0) FANOUT_4 (in_1, {in_1_0, in_1_1, in_1_2, in_1_3, in_1_4, in_1_5, in_1_6});... notg #(0, 0) NOT_1 (WIRE_3, in_1_0); notg #(0, 0) NOT_2 (WIRE_4, out_2_0);... and_n #(3, 0, 0) AND_14 (wire_25, {wire_6_5, wire_3_4, out_2_4}); or_n #(4, 0, 0) OR_2 (wire_21, {wire_25, wire_24, wire_23, wire_22}); dff INS_1 (out_0, wire_1, clk, reset, 1'b0, 1'b1, NbarT, Si, 1'b0); dff INS_2 (out_1,wire_13, clk, reset, 1'b0, 1'b1, NbarT, Si, 1'b0); dff INS_3 (out_2,wire_21, clk, reset, 1'b0, 1'b1, NbarT, Si, 1'b0); endmodule

54 Full Scan Design and Test: Unfolding After synthesis, we start test generation process Circuit in Fig. 33 is a sequential circuit, and test generation methods for sequential circuits are not efficient in terms of fault coverage For this reason, we convert CUT to a combinational circuit by unfolding it, as presented in Fig. 2 Unfolding means removing flip-flops and making their outputs and inputs, pseudo primary inputs and pseudo primary outputs Fig. 34 shows residue5 netlist after being unfolded out 0, out 1, and out 2 that used to be flip-flop outputs are now mapped to PPI0, PPI1, and PPI2 Former flip-flop inputs wire 1, wire 13, and wire 21 are now mapped to PPO1, PPO13, and PPO21 New signals mentioned above also appear on circuit port list as inputs and outputs Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

55 Full Scan Design and Test: Unfolding Figure 34: Unfolded residue5 netlist. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

56 Full Scan Design and Test: Combinational TG Netlist in Fig. 34 represents a combinational circuit We can use random test generation methods and Verilog testbenches for implementing them, as discussed earlier in this course Verilog testbench should generate collapsed fault list before test generation Using combinational test generation will result in 100% fault coverage If we use sequential test generation (as discussed previously), test generation will take longer time (clock cycles), and worse, it will result in less fault coverage Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

57 Full Scan Design and Test: Scan Insertion To facilitate application of tests generated by procedure discussed above to actual CUT, a scan for accessing state flip-flop inputs and outputs is inserted in CUT With insertion of this scan, block diagram of netlist of residue5 becomes as that shown in Fig. 35 For this purpose, postsynthesis netlist of Fig. 33 is modified to include necessary scan flip-flops and signals Synthesis tool, that generated original netlist, used flip-flop types that already included serial shift facilities that were not used in this netlist Fig. 36 shows this flip-flop In Fig. 35 Notation for flip-flop D inputs marked by 1,2D and 1,3D specifies that both D inputs are controlled by clock signal number 1 Upper input requires mode 2 to be active and lower input needs mode 3 Modes 2 and 3 are determined by a 1 or a 0 on lower-left inputs of flip-flop Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

58 Full Scan Design and Test: Scan Insertion Figure 35: residue5 with scan chain. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

59 Full Scan Design and Test: Scan Insertion Figure 36: Flip-flop with scan facilities. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

60 Full Scan Design and Test: Scan Insertion Figure 37: Scan-inserted circuit under test. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

61 Full Scan Design and Test: Scan Insertion Netlist of Fig. 37 Takes advantage of shift features of flip-flop of Fig. 36 This netlist has additional scan control inputs NbarT and Si NbarT input connects to NbarT inputs (shift control) of state flip-flops Si input connects to flip-flop 0 (INS 1), output of which goes to input of the next, eventually forming a chain of three scan flip-flops Signal out 2 that is output of last flip-flop drives So serial output signal Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

62 Full Scan Design and Test: Tester Netlist of Fig. 37 implements original desired functionality of design, as well as our inserted test hardware Once manufactured, it has to be tested with a test plan that depends on test architecture that we have developed, i.e., full scan Test program running on an ATE implements this test plan Block diagram of tester testing full scan version of Residue-5 circuit is shown in Fig. 38 Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

63 Full Scan Design and Test: Tester Figure 38: Tester for residue5. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

64 Full Scan Design and Test: Tester Fig. 38 Main task of tester is to read predetermined test data from an external file, apply it to CUT, get output of CUT, and compare the response with expected response from external file Input data read from test file has two parts One part (PI) is directly applied to circuit s primary inputs, in[1:0] The other (Pseudo PI) is serialized and applied through Si Timing of these data is such that when all serial bits have been shifted in scan chain, parallel data must be applied to in[1:0] Output also has two parts First part (PO) becomes available on out[2:0] immediately after all inputs have been applied State outputs (Pseudo PO) become available after flip-flops have been clocked and then shifted out through So Arrangement of inputs and outputs in a line read from test file is shown in Fig. 39 Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

65 Full Scan Design and Test: Tester Figure 39: Arrangement of stimulus and response in line. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

66 Scan Architectures Full scan is part of a larger category of DFT techniques that are referred to as scan architectures Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

67 Scan Architectures: Full Scan Design Full scan DFT technique Feedback registers are given additional capability of acting as shift-registers in test mode Full scan chains all registers together and provides a serial-in and a serial-out ports This method enables serial access for controlling all flip-flop outputs (circuit s present state) and observing all flip-flop inputs (circuit s next state) Full scan refers to the fact that all circuit flip-flops are included in scan chain Problem with full scan is long chain of flip-flops that test data have to be shifted into that reflects on test time Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

68 Scan Architectures: Full Scan Design Figure 40: Huffman model with multiple vector inputs, outputs, and states. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

69 Scan Architectures: Full Scan Design Figure 41: Full scan DFT technique. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

70 Scan Architectures: Shadow Register DFT An alternative design to full scan design is use of shadow registers This technique duplicates feedback registers It uses one set for normal operation of circuit and another set for test purposes This method reduces test time by overlapping time of test data preparation and response collection with normal operation of circuit Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

71 Scan Architectures: Shadow Register DFT Figure 42: Shadow register. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

72 Scan Architectures: Shadow Register DFT Shadow test procedure Normal mode NbarT = 0 Circuit has its normal inputs, and normal feedback registers provide data for present state of circuit Shadow registers are put in their serial shift mode Therefore, simultaneous with normal operation, test data on Si are shifted into shadow registers with Tclk When all test data are shifted in, NbarT is asserted Test mode NbarT = 1 disables shifting serial data into shadow register, and disables clk, and test states (TS1 and TS2) will drive ps1 and ps2 We also drive PI1 and PI2 with their corresponding test data With test inputs provided to all combinational block inputs, response becomes available on PO1, PO2, ns1, and ns2 Primary output part of response (PO1 and PO2) can be read at this time Clocking circuit loads ns1 and ns2 into shadow registers NbarT = 0 clk is enabled and circuit is put in normal mode this puts shadow registers in shift mode new test data inputs are shifted from Si, and part of test response on ns1 and ns2 are shifted out via So Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

73 Scan Architectures: Shadow Register DFT Shadow vs. full scan The biggest advantage of shadow registers is capability of online testing Its disadvantage is doubling the number of feedback flip-flops Timing Having a separate clock for test (Tclk) enables faster shifting of test data into shadow registers On the other hand, multiplexers in feedback path cause a delay in this path This delay slows down normal clock speed and affects system performance For test generation, combinational methods can be used with unfolded version of CUT This is because insertion of shadow registers makes all combinational part inputs and outputs accessible Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

74 Scan Architectures: Partial Scan Methods Partial scan Problem of test time in full scan designs can be alleviated by scan chains that include only part of feedback registers Method of selecting registers that are put in scan varies from one partial scan method to another But in general, selection must be done such that combinational test generation methods can still be used for test data generation Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

75 Scan Architectures: Partial Scan Methods Figure 43: Partial scan, starting with Huffman model. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

76 Scan Architectures: Partial Scan Methods Figure 44: Partial scan datapath. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

77 Scan Architectures: Partial Scan Methods Fig. 43 or 44 We assume combinational part of circuit consists of two combinational blocks Circuit primary inputs split and go to both blocks, A and B, and outputs of blocks form circuit s primary outputs Partial scan is possible in this circuit because One feedback register is driven by block A; output of this register goes to input of block B The other feedback register is driven by block B; output of this register goes to block A To test all logic in this circuit, it is only necessary to put feedback register R2 in a scan path Removal of R1 from full scan would still qualify resulting circuit model for combinational test generation Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

78 Scan Architectures: Partial Scan Methods Test generation for combinational part of circuit of Fig. 43 (or 44) is done by a circuit model that removes R1, and then unfolds circuit This combinational model is shown in Fig. 45 Since this model does not have any feedback loops, it is treated as a combinational circuit Figure 46: Test vector arrangement. Figure 45: Partial scan combinational model. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

79 Scan Architectures: Partial Scan Methods Partial scan test procedure NbarT = 1 R1 disabled Clock R2, shift PPI1 test data into R2, also of previous test serially collect PPO1 Apply PI1 test data to PI1 input, collect response from PO1 NbarT = 0 R1 enabled, clock once Apply PI2 test data to PI2 input, collect response from PO2 Clock once Return to step 1 Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

80 Scan Architectures: Partial Scan Methods Partial scan vs. full scan Partial scan reduces test time by having fewer bits to shift in On the other hand, partial scan has a more complex test procedure The main problem is that there is no unique partial scan method, and not all circuits can take advantage of a partial scan method For finding proper registers to scan, a topological processing of circuit is necessary A partial scan method fits well with pipeline architectures In this case, test procedure becomes dependent on depth of pipeline Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

81 Scan Architectures: Multiple Scan Design Problem of long scan chain can be moderated by using multiple independent or parallel scan chains Multiple independent scan chains Each scan register has its shift, load, and clock control If the number of flip-flops in scan chains in a design are not the same, they need independent shift and clock enable control signals Multiple parallel scan chains All scan registers are controlled by the same set of signals If registers to be scanned can be put into groups of equal number of cells, they can be regarded as parallel scan registers with the same set of control signals Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

82 Scan Architectures: Multiple Scan Design Figure 47: Multiple parallel scan chains. Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

83 Scan Architectures: Multiple Scan Design Fig. 47 R1 and R2 are put into two separate scan chains with Si1 and Si2 inputs and So1 and So2 outputs Registers R1 and R2 have the same length Therefore, scan chains are two parallel registers with the same clock and NbarT control inputs Multiple scan test procedure (Fig. 47) Input test data consist of PI1, PI2, PPI1, PPI2 Test responses consist of PO1, PO2, PPO1, PPO2 For testing, NbarT = 1 R1 and R2 are in shift mode Individual test data bits from corresponding test data segments (PPI1 and PPI2) are read and applied simultaneously to Si1 and Si2 While shifting-in occurs, previous results are collected from So1 and So2 When shifting is complete, NbarT = 0, parallel test data for PI1 and PI2 are applied, and PO1 and PO2 are read Clock once, return to step 1 Multiple scan features (compared with full scan) Significantly reduces test time Its test generation is no different than that for full scan Needs extra test pins, and for independent scans, extra controls Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84

84 References Zainalabedin Navabi, Digital System Test and Testable Design: Using HDL Models and Architectures, Springer, Moslem Amiri, Václav Přenosil Digital Systems Testing December, / 84