Design of a Self Checking Up Counter

Transcription

1 Desin o a Sel Checkin Up Counter KHADIJA F. O. ALGHEITTA khaitta@yahoo.com AMAL J. MAHFOUD amal_11081@yahoo.com ALI H. MAAMAR ali_h_maamar@yahoo.co.uk Department o Computer Enineerin, Faculty o Electronic Technoloy Beni Waled, LIBYA Abstract: A reister that oes throuh a sequence o distinct states upon the application o a sequence o input pulses is called a counter. Counters which count upward rom zero to maximum are called binary counter. In this counter the ability o aults are available [1]. The characteristics o these types o aults render them undetectable by standard test strateies. The detection o intermittent aults requires the use o Concurrent Error Detection (CED) technique, which continuously monitors the operation o circuits and compares them with some known reerence. This is achieved by incorporatin some orm o redundancy into the system [2]. One method o implementin CED in VLSI circuit is throuh the use o inormation redundancy. This paper investiates the use o inormation redundancy into unchecked system as a mean o incorporatin CED into a sel-checkin binary counter. Key-Words: binary counter, Sel checkin, Concurrent Error Detection, Inormation Redundancy. 1. Introduction Unortunately as the scale o interation has increased so also has the occurrence o intermittent aults. The characteristics o these types o aults render them undetectable by standard test strateies. The detection o intermittent aults requires the use o Concurrent Error Detection (CED) techniques, which continually monitor the operation o the circuit and compared it with some known reerence; this is achieved by incorporatin some orm o redundancy into the system [2]. One method o implementin CED in VLSI circuit is throuh the use o inormation redundancy. This paper investiates the use o inormation redundancy into unchecked system as a mean o incorporatin CED into a sel-checkin up counter. Sel-checkin circuit can be deined as the ability to veriy automatically whether there is any ault in the circuit (chips, boards, or assembled system), thus, sel-checkin circuits allow on-line error detection, which means aults can be detected durin the normal operation o the circuit [3]. The sel-checkin could be achieved by the redundancy techniques; one way to achieve sel-checkin desin is throuh the use o error detectin codes (the inormation redundancy technique) [4]. : ), Volume : 11 Issue :

2 2. Up Counter The up counter is a normal counter, that counts up or incremented its present state when it receives count up sinal, its next state at any time is equal to the present state o the counter +1, or example i the present state o the counter is 1001, then the next state is The counter is active only when the control is hih, as the new value o the up counter has to be compared with the value o the up counter, i the two values are not match an error sinal is enerated, which means the up counter did not counts correctly, or the up counter itsel did a mistake, in both cases an error sinal should be activated. When the up counter receives reset sinal it oes back to zero not to 1. The up counter is a normal counter, it updates itsel accordin to the control sinals (up and reset), when it receives up sinal the present state o the counter is incremented by 1, and the reset sinal sets all bits o the counter to zero. Fiure 1, shows the typical waveorm o the up counter. Fi. 1, the typical waveorm o the up counter. 3. Berer Code Berer code is a separable and unordered code, it is separable because the inormation bits and the check bits (check symbol) in the codeword are separate, it is an unordered code as it is not possible to chane one codeword into another codeword by simply chanin either 1's to 0's or 0's to 1's, this means that the code can detect all unidirectional errors. The codeword o the Berer code is ormed by appendin the check bits to the inormation bits, the check bits o the code is the binary representation o the number o 1's (or the complement o the number o 0's) in the inormation bits, the number o check bits k Lo2 I 1 (data word), the number o bits in the codeword n I k bits., where I is the number o bits in the inormation bits k I the number o inormation bits in a codeword is I 2 1, k 1 then the code is known as a Maximal Lenth Berer code; otherwise it is known as a Non Maximum Lenth Berer code. : ), Volume : 11 Issue :

3 For example, i I 7 and k 3, it is Maximal Lenth Berer code because 2 1 k k 3 is Non-Maximal Lenth Berer code because I 2 1 k. I, whereas I 6 and 4. Sel Checkin Circuits Sel-checkin circuits allow on-line error detection that means aults can be detected durin the normal operation o the circuit. It can detect the presence o both transient and permanent aults. A sel-checkin circuit, see iure 2, consists o a unctional circuit (F), which produces encoded output vectors, and a checker (C), which checks the vectors to determine i an error has occurred. The checker has the ability to ive an error indication even when a ault occurs in the checker itsel. Fi.2 General structure o sel-checkin circuit Sel-checkin loic is typically desined usin codin techniques; one way to achieve sel-checkin desin is throuh the use o error detectin codes (the inormation redundancy technique). 5. Checker Circuit There are two identical check symbol enerator circuits used in the sel checkin up counter, the irst checker which used to enerate the check symbol o the contents o the counter, and the second used to enerate the check symbol o the present state +1. The output o the check symbol enerator which is the Berer code check symbol, and the output o the predicted Berer code check symbol are both ed to the Two Real Checker. The checker circuit is a normal Two-Rail checker (TRC) iure 3, the TRC is used to compare two complementary binary values. The checker determines whether the output o the unctional circuit is a valid or invalid. Two-rail checker unit has two roups o inputs: (x 1,x 2,..x n) and (y 1,y 2,..y n). It also has two outputs: and. The sinals observed on the outputs should always be complementary. Consider a two rail checker with n=2, as shown in Fiure 3, the two input roups are (x 1,x 2) and (y 1,y 2). In a non-error situation where (y 1=x 1') and (y 2=x 2'), the result o this is (='). In situation where due to a ault where (y 1=x 1) or (y 2=x 2), this will then produce (=), that means a valid output thus ivin an error sinal. : ), Volume : 11 Issue :

4 Fi.3 Two rail checker with 2 pairs o inputs 5. Sel checkin hardware The hardware o the checker circuit depends on the type o the redundancy to be used, whether it is a hardware redundancy, inormation redundancy, or time redundancy. In this paper an inormation redundancy will be used in the desin o sel checkin up counter. Fiure 4 shows a block diaram o a sel checkin up counter. The extra hardware needed as shown in iure4, consists o reister, and checkers. The checkers are, Check symbol enerator, which enerates the check symbol o Berer code or the new value o the present state o the counter, and the other check symbol enerator is also Berer code check symbol enerator, which enerate the predicted check symbol, or the present state +1, or example, when the counter is at 0000 state, then there are two check symbols, enerated, one is or state 0000, and the other or state 0001 (predicted check symbol). When count up sinal is enerated, the counter oes to state 0001, and the check symbol enerator enerates the check symbol or state 0001, and compared with the predicted check symbol which enerated in the previous state, i the match then no error occurred, and new check symbol ( predicted check symbol) or state 0010 is enerated. But i an error detected then the counter did not count correctly, and an error sinal enerated. In eneral, the check symbol enerator enerates the check symbol or the new state, and the predicted check symbol enerator enerates the predicted check symbol, which in act is the check symbol or the next state o the counter. Clk Reset Up U1 clk count(7:0) reset up up_counter U2 clk CB(3:0) reset up Re_CB count(7:0) U3 I(7:0) k(3:0) CSB_8_bits CB(3:0) k(3:0) k(3) k(2) CB(3) CB(2) k(1) k(0) CB(1) CB(0) U4 T_R U5 T_R U6 T_R_C Fi.4 sel checkin up counter Fiure 5, shows the typical waveorm o the counters. CLK sinal is ree runnin. The counter counts the new values by a risin ede on the CLK line. : ), Volume : 11 Issue :

5 Fi.5 Timin diaram o the sel checkin up counter 5. Conclusions: The sel checkin up counter presented in this paper was desined and simulated usin HDL lanuae. Sel checkin achieved by usin Berer code, as the counter always chanes its state, the new state checked beore it can be accepted as true state. Incorporated Concurrent Error Detection techniques is not ree, the price an extra hard ware and a tie delay. The extra hard ware is the hard ware to desin two Berer code check symbol enerators, and two rail checker. Reerences: [1] M. Morris Mano and Charles R. Kime "Loic and Computer Desin Fundamentals" by Prentice Hall, 3 rd edition, chapter 7.p331. [2] Russell, G.; Maamar, A.H., "Check bit prediction scheme usin Don's code or concurrent error detection in VLSI processors," Computers and Diital Techniques, IEE Proceedins -, vol.147, no.6, pp , Nov [3] Miron Abramovici, Melvin A.Breuer, and Arthur D.Friedman, "Diital Systems Testin and Testable Desin,1990,ISBN , Chapter 13:SELF-CHECKING DESIGN, pp [4] Huda Abuharsa, and Ali Maamar," Sel Checkin Systolic LIFO Stack",7th WSEAS Int. Con. on Instrumentation, Measurement, Circuits and Systems (IMCAS '08), Hanzhou, China, April 6-8,2008. [5]M.MORRIS MANO, Diital Desin, 2002, 1991, 1984 by Prentice Hall, Upper Saddle River, New Jersey 07458, Chapter 6, P234. [6] Michael D.Ciletti, "Advanced Diital Desin with the Verilo HDL", Upper Saddle River, New Jersey, Chapter 9, pp : ), Volume : 11 Issue :