ICS Pentium/Pro TM System Clock Chip. Integrated Circuit Systems, Inc. General Description. Pin Configuration.

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1 Interated Circuit Systems, Inc. ICS948-8 Pentium/Pro TM System Clock Chip General Description The ICS948-8 is a Clock Synthesizer chip for Pentium and PentiumPro CPU based Desktop/Notebook systems that will provide all necessary clock timin. Features include two CPU and six PCI clocks. One reference output is available equal to the crystal frequency. Additionally, the device meets the Pentium power-up stabilization requirement, acheivin stable CPU and PCI clocks 2ms after power-up. PD# pin can enable a low power mode by stoppin crystal OSC and PLL staes. Other power manaement features include, CPU_STOP# which stops CPU (0:) clocks, and PCI_STOP# which stops PCICLK (0:4) clocks. Hih drive CPUCLK outputs typically provide reater than V/ns slew rate into 20pF loads. PCICLK outputs typically provide better than V/ns slew rate into 30pF loads while maintainin 50±5% duty cycle. The REF clock output typically provides better than 0.5V/ns slew rates. Features Generates system clocks for CPU, PCI, plus 4.34 MHz REF0. Supports sinle or dual processor systems Skew from CPU (earlier) to PCI clock (risin edes for 00/33.3MHz) to 4ns Separate 2.5V and 3.3V supply pins 2.5V or 3.3V output: CPU 3.3V outputs: PCI, REF No power supply sequence requirements Uses external 4.38MHz crystal, no external load cap required for C L =8pF crystal 28 pin 209 mil SSOP Pin Confiuration The ICS948-8 accepts a 4.38MHz reference crystal or clock as its input and runs on a 3.3V core supply. Block Diaram 28 pin SSOP Power Groups VDD = Supply for PLL core VDD = REF0, X, X2 VDD2 = PCICLK_F, PCICLK (0:4) VDDL = CPUCLK (0:) Ground Groups GND = Ground Source Core GND = REF0, X, X2 GND2 = PCICLK_F, PCICLK (0:4) GNDL = CPUCLK (0:) Pentium is a trademark on Intel Corporation Rev C 2/02/05 ICS reserves the riht to make chanes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information bein relied upon by the customer is current and accurate.

2 ICS948-8 Pin Descriptions PIN NUMBER PIN NAME 26 REF0 28 GND X 2 X2 3, 2 GND2 4 PCICLK_ F 5, 7, 8, 0, PCICLK (0:4) 6, 9 VDD2 3, 2 VDD 4, 20 GND 5 SEL00/66.6# 6 FS0 7 PD# 8 CPU_STOP# 9 PCI_STOP# 25 VDDL 22 GNDL 23, 24 CPUCLK (:0) 27 VDD TYP E OUT PWR IN OUT PWR OUT OUT PWR PWR PWR DESCRIPTIO N 4.38MHz clock output Ground for REF outputs XTAL_IN 4.38MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Free PCI output PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Isolated power for core, nominally 3.3V Isolated round for core Select pin for enablin 00MHz or 66.6MHz IN H=00MHz, L=66.6MHz (PCI always synchronous 33.3MHz) IN Frequency Select pin IN Powers down chip, active low IN Halts CPU clocks at loic "0" level when low IN Halts PCI Bus at loic "0" level when low PWR Power for CPU outputs, nominally 2.5V P WR Ground for CPU outputs. OUT CPU and Host clock 2.5V P WR Power for REF outputs. Select Functions (Functionality determined by FS0 and SEL00/66# pin, see below) Functionality CPUCL K PCI, PCI_ F REF0 Tristate HI - Z HI - Z HI - Z Testmode TCLK/ 2 TCLK/ 6 TCLK Notes:. TCLK is a test clock driven on the X (crystal in pin) input durin test mode. SEL 00/66# FS0 Functio n 0 0 Tri-Stat e 0 - (Reserved ) 0 - (Reserved ) 0 Active 66.6MHz CPU, 33.3 PCI 0 Test Mode - (Reserved ) - (Reserved ) Active 00MHz CPU, 33.3 PCI 2

3 ICS948-8 Technical Pin Function Descriptions VDD(,2) This is the power supply to the internal core loic of the device as well as the clock output buffers for REF0, PCICLK (0:4), and PCICLK_F. This pin operates at 3.3V volts. Clocks from the buffers that it supplies will have a voltae swin from Ground to this level. For the actual uaranteed hih and low voltae levels for the clocks, please consult the DC parameter table in this data sheet. VDDL This is the power supply for the CPUCLK output buffers. The voltae level for these outputs may be 2.5 or 3.3volts. Clocks from the buffers that this pin supplies will have a voltae swin from Ground to VDDL. For the actual uaranteed hih and low voltae levels of these Clocks, please consult the DC parameter table in this data sheet. GND(,2) This is the power supply round (common or neative) return pin for the internal core loic and all the PCI output buffers. GNDL This is the round for CPUCLK output buffers. X This input pin serves one of two functions. When the device is used with a crystal, X acts as the input pin for the reference sinal that comes from the crystal. When the device is driven by an external clock sinal, X is the device input pin for that reference clock. This pin also has an internal Crystal loadin capacitor that is connected to round. With a nominal value of 33pF, no external load cap is needed for a C L =7 to 8pF crystal. X2 This Output pin is used only when the device uses a crystal as the reference frequency source. In this mode of operation, X2 is an output sinal that drives (or excites) the crystal. The X2 pin also has an internal loadin capacitor, nominally 33pF. REF0 The REF Output is fixed frequency clock that runs at the same frequency as the Input Reference Clock or the Crystal (typically 4.388MHz) attached across X and X2. PCICLK_F This Output is equal to PCICLK(0:4) and is FREE RUNNING, and will not be stopped by PCI_STOP#. PCICLK (0:4) These output clocks enerate all the PCI timin requirements for a Pentium/Pro based system. They conform to the current PCI specification. SELECT 00/66.6MHz# This input pin controls the frequency of the clocks at the CPU & PCICLK output pins. If a loic value is present on this pin, the 00MHz clock is selected. If a loic 0 is used, the 66.6MHz frequency is selected. The PCI clock is multiplexed to run at 33.3MHz for both select cases. PCI is synchronous at the risin ede of PCI to the CPU risin ede (with the skew makin CPU early). PD# This is an asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and Crystal are stopped. Power down will also place all the outputs in a low state at the end of their current cycle. The latency of power down will not be reater than 3ms. CPU_STOP# This is a synchronous active low input pin used to stop the CPUCLK clocks in an active low state. All other clocks will continue to run while this function is enabled. The CPUCLKs will have a turn ON latency of at least 3 CPU clocks. PCI_STOP# This is a synchronous active low input pin used to stop the PCICLK clocks in an active low state. It will not effect PCICLK_F nor any other outputs. CPUCLK (0:) These output pins are the clock outputs that drive processor and other CPU related circuitry that requires clocks which are in tiht skew tolerance with the CPU clock. The voltae swin of these clocks is controlled by the voltae level applied to the VDDL pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these clocks and the selection codes to produce them. 3

4 ICS948-8 Power Manaement Clock Enable Confiuration CPU_STO- P# PCI_STOP# PWR_DW- N# CPUCLK X X 0 Low 0 0 Low 0 Low 0 00/66.6MHz 00/66.6MHz PCICLK Low Low 3.3 MHz Lo 3.3 MH REF Stopped 3 w 3 z Crystal Off VCOs Off Full clock cycle timin is uaranteed at all times after the system has initially powered up except where noted. Durin power up and power down operations usin the PD# pin will not cause clocks of a short or loner pulse than that of the runnin clock. The first clock pulse comin out of a stopped clock condition may be slihtly distorted due to clock network charin circuitry. Board routin and sinal loadin may have a lare impact on the initial clock distortion also. ICS948-8 Power Manaement Requirements SIGNAL SIGNAL STAT E Latency No. of risin edes of free runnin PCICLK C PU_ STOP# 2 0 (Disabled ) (Enabled) P CI_STOP# 2 0 (Disabled ) PD# (Enabled) (Normal 3 Operation) 3ms 4 0 (Power Down) 2max Notes.. Clock on latency is defined from when the clock enable oes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable oes inactive to when the last clock is driven low out of the device. 3. Power up latency is when PD# oes inactive (hih) to when the first valid clocks are output by the device. 4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only. The REF and IOAPIC will be stopped independant of these. 4

5 ICS948-8 CPU_STOP# Timin Diaram CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS The minimum that the CPUCLK is enabled (CPU_STOP# hih pulse) is 00 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that uarantees the hih pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs. Notes:. All timin is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This sinal is synchronized to the CPUCLKs inside the ICS All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a hih (true) state. PCI_STOP# Timin Diaram PCI_STOP# is an asynchronous input to the ICS It is used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS948-8 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP# hih pulse) is at least 0 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full hih pulse width uaranteed. PCICLK (0:4) clock on latency cycles are only one risin PCICLK clock off latency is one PCICLK clock. Notes:. All timin is referenced to the Internal CPUCLK (defined as inside the ICS948 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This sinal is required to be synchronized inside the ICS All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a hih (true) state. 5

6 ICS948-8 PD# Timin Diaram The power down selection is used to put the part into a very low power state without turnin off the power to the part. PD# is an asynchronous active low input. This sinal is synchronized internally by the ICS948-8 prior to its control action of powerin down the clock synthesizer. Internal clocks will not be runnin after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turnin off the VCOs and the crystal oscillator. The power on latency is uaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are don t care sinals durin the power down operations. Notes:. All timin is referenced to the Internal CPUCLK (defined as inside the ICS948 device). 2. PD# is an asynchronous input and metastable conditions may exist. This sinal is synchronized inside the ICS The shaded sections on the VCO and the Crystal sinals indicate an active clock is bein enerated. 6

7 ICS948-8 Absolute Maximum Ratins Supply Voltae V Loic Inputs GND 0.5 V to V DD +0.5 V Ambient Operatin Temperature C to +70 C Storae Temperature C to +50 C Stresses above those listed under Absolute Maximum Ratins may cause permanent damae to the device. These ratins are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum ratin conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0-70C; Supply Voltae VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Hih Voltae VIH 2 VDD+0.3 V Input Low Voltae VIL VSS V Input Hih Current IIH VIN = VDD 0. 5 µa Input Low Current IIL VIN = 0 V; Inputs with no pull-up resistors µa Operatin IDD3.0(66) CL = 0 pf; 66MHz ma Supply Current IDD3.3(00) CL = 0 pf; 00MHz Power Down IDD3.3PD CL = 0 pf µa Supply Current Input frequency Fi VDD = 3.3 V; All outputs loaded 4.38 MHz Input Capacitance CIN Loic Inputs 5 pf CINX X & X2 pins pf Transition Time Ttrans To st crossin of taret Freq. 3 ms Settlin Time Ts From st crossin to % taret Freq. 5 ms Clk Stabilization TSTAB From VDD = 3.3 V to % taret Freq. 3 ms Skew TCP U-P CI VT =.5 V; ns Guaranteed by desin, not 00% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0-70C; Supply Voltae VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operatin IDD2.5(66) CL = 0 pf; 66.8 MHz 3 25 ma Supply Current IDD2.5(00) CL = 0 pf; 00 MHz 4 25 ma Power Down IDD2.5PD CL = 0 pf 00 µa Supply Current Skew tcpu-pci2 VT =.5 V; VTL =.25 V ns Guaranteed by desin, not 00% tested in production. 7

8 ICS948-8 Electrical Characteristics - CPUCLK TA = 0-70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 0-20 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance RDSP2B VO = VDD*(0.5) Ω Output Impedance RDSN2B VO = VDD*(0.5) Ω Output Hih Voltae VOH2B IOH = -2.0 ma V Output Low Voltae VOL2B IOL = 2 ma V Output Hih Current IOH2B VOH =.7 V -4-9 ma Output Low Current IOL2B VOL = 0.7 V 9 37 ma Rise Time tr2b VOL = 0.4 V, VOH = 2.0 V.2.6 ns Fall Time tf2b VOH = 2.0 V, VOL = 0.4 V.6 ns Duty Cycle dt2b VT =.25 V % Skew tsk2b VT =.25 V ps Jitter, Cycle-to-cycle tjcyc-cyc2b VT =.25 V ps Jitter, One Sima tjs2b VT =.25 V ps Jitter, Absolute tjabs2b VT =.25 V ps Guaranteed by desin, not 00% tested in production. Electrical Characteristics - REF0 TA = 0-70C; VDD = VDDL = 3.3 V +/-5%; CL = 0-20 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance RDSP5 VO = VDD*(0.5) Ohm Output Impedance RDSN5 VO = VDD*(0.5) Ohm Output Hih Voltae VOH5 IOH = -2 ma V Output Low Voltae VOL5 IOL = 9 ma V Output Hih Current IOH5 VOH = 2.0 V ma Output Low Current IOL5 VOL = 0.8 V 6 42 ma Rise Time tr5 VOL = 0.4 V, VOH = 2.4 V ns Fall Time tf5 VOH = 2.4 V, VOL = 0.4 V ns Duty Cycle dt5 VT =.5 V % Jitter, One Sima tjs5 VT =.5 V 3 % Jitter, Absolute tjabs5 VT =.5 V 3 5 % Guaranteed by desin, not 00% tested in production. 8

9 ICS948-8 Electrical Characteristics - PCICLK TA = 0-70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pf PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance RDSP VO = VDD*(0.5) 2 55 Ω Output Impedance RDSN VO = VDD*(0.5) 2 55 Ω Output Hih Voltae VOH IOH = - ma V Output Low Voltae VOL IOL = 9.4 ma V Output Hih Current IOH VOH = 2.0 V ma Output Low Current IOL VOL = 0.8 V 6 57 ma Rise Time tr VOL = 0.4 V, VOH = 2.4 V. 2 ns Fall Time tf VOH = 2.4 V, VOL = 0.4 V.3 2 ns Duty Cycle dt VT =.5 V % Skew tsk VT =.5 V ps Jitter, One Sima tjs VT =.5 V 3 50 ps Jitter, Absolute tjabs VT =.5 V ps Guaranteed by desin, not 00% tested in production. 9

10 ICS948-8 General Layout Precautions: ) Use a round plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: All clock outputs should have series terminatin resistor. Not shown in all places to improve readibility of diaram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended. Capacitor Values: C, C2 : Crystal load values determined by user C3 : 00pF ceramic All unmarked capacitors are 0.0µF ceramic 0

11 ICS948-8 COMMON VARIATIONS D SYMBOL DIMENSIONS M IN. N OM. MAX. N M IN. N OM. MAX. A A A b c D See Variations E e BSC H L N See Variations Dimensions in inches Orderin Information ICS948F-8LF Example: ICS XXXX F - PPP LF Lead Free, RoHS Compliant (Optional) Pattern Number (2 or 3 diit number for parts with ROM code patterns) Packae Type F=SSOP Device Type (consists of 3 or 4 diit numbers) Prefix ICS, AV = Standard Device ICS reserves the riht to make chanes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information bein relied upon by the customer is current and accurate.

12 ICS948-8 Revision History Rev. Issue Date Description Pae # C 2/2/2005 Added LF Orderin Information 2