Electronic Technology Design and Workshop

Transcription

1 IFE, B&T, V semester Electronic Technology Design and Workshop Presented and updated by Przemek Sekalski DMCS room

2 IFE, B&T, V semester Electronic Technology Design and Workshop Lecture 4 Introduction to Microelectronics

3 IFE, B&T, V semester 3 ETDW course road map Schematic edition, libraries of elements Circuit simulation & netlist generation Microelectronics - full custom design and simulation Microelectronics - simple layout synthesis Hardware description languages - behavioural description Logic & sequential synthesis - programmable logic devices PCB design auto-routing Project - bringing the pieces together

4 IFE, B&T, V semester 4 What is Microelectronics? MICROELECTRONICS [gr.], part of electronics considering behavior, constructions and fabrication technology of integrated circuits

5 IFE, B&T, V semester 5 What is integrated circuit? INTEGRATED CIRCUIT, electronic device (microchip), where some or all components including interconnections are fabricated during single technological process in the single silicon substrate.

6 IFE, B&T, V semester 6 Integrated Circuit Types Hybrid Thick Layer Thin Layer Monolithic

7 IFE, B&T, V semester 7 Thick Layer Integrated Circuits Wire loop connections Semiconductor devices without the cover (no encapsulation) Bonding Wire tape connections Semiconductor devices with cover (encapsulated) Substrate Thin layer resistor Discrete Capacitor Soldering

8 IFE, B&T, V semester 8 Thick Layer Integrated Circuits

9 IFE, B&T, V semester 9 Thin Layer Integrated Circuits i.e. thin-film transistor (TFT)

10 IFE, B&T, V semester 10 TFT (1)

11 IFE, B&T, V semester 11 TFT (2)

12 IFE, B&T, V semester 12 TFT (3)

13 IFE, B&T, V semester 13 TFT (4)

14 IFE, B&T, V semester 14 Monolithic Integrated Circuits

15 IFE, B&T, V semester 15 Integrated Circuits Advantages Low cost Small dimensions Reliability Identity of temperature characteristics

16 IFE, B&T, V semester 16 Monolithic Integrated Circuits Standard Application Specific (ASIC)

17 IFE, B&T, V semester 17 Standard Circuits Advantages Low cost off shelf accessibility Verified reliability Many suppliers and manufacturers (usually)

18 IFE, B&T, V semester 18 Standard Circuits Disadvantages Not optimized for specific problems Large area occupation

19 IFE, B&T, V semester 19 ASIC Advantages Easy parameter optimization for specific system Effective area usage Higher reliability and decreased number of devices on board

20 IFE, B&T, V semester 20 ASIC Disadvantages High cost for low series High project costs Single Supplier Long designing time

21 IFE, B&T, V semester 21 Specialized Circuits Programmable (FPLD) Semi-custom Custom

22 IFE, B&T, V semester 22 Field Programmable Logic Devices Writable Writable / erasable Volatile

23 IFE, B&T, V semester 23 Field Engineer

24 IFE, B&T, V semester 24 Semi-custom circuits Gate array Linear array

25 IFE, B&T, V semester 25 Custom Circuits Standard Cell Full Custom

26 IFE, B&T, V semester 26 Designer Tasks Draw the circuit Draw the state diagram Describe behavior using high level language i.e. VHDL or Verilog Draw masks of integrated circuit

27 IFE, B&T, V semester 27 Designer Task Draw masks of integrated circuit

28 IFE, B&T, V semester 28 Design Tools Xilinx Synopsis/Viewlogic Compass Cadence Mentor Graphics

29 IFE, B&T, V semester 29 Design tools functions Edition of text, circuit scheme, topography Synthesis Topography and scheme comparison Design rules checking Component positioning and interconnecting Simulation

30 IFE, B&T, V semester 30 MOS TRANSISTOR (Metal-Oxide-Semiconductor) BASICS

31 IFE, B&T, V semester 31 MOS Transistor Symbols Enhanced Mode n-type Transistor G D B S D B S G D S Enhanced Mode p-type Transistor Depleted Mode n-type Transistor Depleted Mode p-type Transistor

32 IFE, B&T, V semester 32 MOS Transistor Polisilicon gate Dielectric Metal elctrode Drain and source area Silicon substrate

33 IFE, B&T, V semester 33 nmos Transistor physical structure Enhancement-type NMOS transistor: (a) perspective view (b) cross section Typically L = 1 to 10 µm, W = 2 to 500 µm, and the thickness of the oxide layer is in the range of 0.02 to 0.1 µm.

34 IFE, B&T, V semester 34 nmos Transistor cross-section Źródło Source Bramka Gate Dren Drain Metal Polysilicon Silicon dioxide N-type diffusion P-type substrate

35 IFE, B&T, V semester 35 nmos Transistor with polarised gate cross-section Source Źródło Bramka Gate Drain Dren Metal Polysilicon Silicon dioxide N-type diffusion P-type substrate Channel

36 IFE, B&T, V semester 36 nmos operation - positive voltage applied to the gate An n channel is induced at the top of the substrate beneath the gate.

37 IFE, B&T, V semester 37 nmos operation - V GS > V t and with a small V DS applied The device acts as a conductance whose value is determined by v GS. Specifically, the channel conductance is proportional to v GS - V t, and this i D is proportional to (v GS - Vt) v DS. Note that the depletion region is not shown (for simplicity).

38 IFE, B&T, V semester 38 nmos Transistor In Linear Range Source Źródło Bramka Gate Drain Dren Metal Polysilicon Silicon dioxide N-type diffusion P-type substrate Channel

39 IFE, B&T, V semester 39 nmos operation - V DS is increased The induced channel acquires a tapered shape and its resistance increases as v DS is increased. Here, v GS is kept constant at a value > V t.

40 IFE, B&T, V semester 40 The drain current versus the drain-to-source voltage V DS V GS > V t.

41 IFE, B&T, V semester 41 nmos Transistor Near The Saturation Bramka Gate Źródło Source Dren Drain Metal Polysilicon Silicon dioxide N-type diffusion P-type substrate Channel

42 IFE, B&T, V semester 42 nmos transistor operation output characteristic The output (i D v DS )characteristics for a device with V t = 1 V and k n (W/L) = 0.5 ma/v 2.

43 IFE, B&T, V semester 43 Saturated nmos Transistor Source Źródło Gate Bramka A Drain Dren Metal Polysilicon Silicon dioxide N-type diffusion P-type substrate Channel

44 IFE, B&T, V semester 44 Saturated nmos Transistor Fig Increasing v DS beyond v DSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by L).

45 IFE, B&T, V semester 45 Fig (a) An n-channel enhancement-type MOSFET with v GS and v DS applied and with the normal directions of current flow indicated. (b) The i D - v DS characteristics for a device with V t = 1 V and k n (W/L) = 0.5 ma/v 2. Fig The i D - v GS characteristic for an enhancement-type NMOS transistor in saturation (V t = 1 V and k n (W/L) = 0.5 ma/v 2 ).

46 IFE, B&T, V semester 46 Fig Effect of v DS on i D in the saturation region. The MOSFET parameter V A is typically in the range of 30 to 200 V.

47 IFE, B&T, V semester 47 Depletion-type n-channel MOSFET Fig The current-voltage characteristics of a depletion-type n-channel MOSFET for which V t = -4 V and k n (W/L) = 2 ma/v 2 : (a) transistor with current and voltage polarities indicated; (b) the i D - v DS characteristics; (c) the i D - v GS characteristic in saturation.

48 IFE, B&T, V semester 48 MOS Transistor Symbols Enhanced Mode n-type Transistor G D B S D B S G D S Enhanced Mode p-type Transistor Depleted Mode n-type Transistor Depleted Mode p-type Transistor

49 IFE, B&T, V semester 49 nmos Transistor As a Switch + 5V + 5V

50 IFE, B&T, V semester 50 pmos Transistor As a Switch + 5V + 5V

51 IFE, B&T, V semester 51 MOS Transistor Capacitances GATE BRAMKA C GSov C GS C GD C GDov SOURCE ŹRÓDŁO DRAIN DREN C BS C GB C BD

52 IFE, B&T, V semester 52 MOS Transistor - summary Zakres pracy Zakres odcięcia, nieprzewodzenia Zakres liniowy, nienasycenia, triodowy Zakres nasycenia, pentodowy Zakres podprogowy, słabej inwersji Napięcia na końcówkach U GS <U FB U GS V T i U DS <U Dsat U GS V T i U DS U Dsat U FB U GS <V T Enhanced Kanał Mode wzbogacany n-type Transistor typu n I DS U GS I DS U DS I DS U GS I DS Enhanced Kanał Mode wzbogacany p-type Transistor typu p U DS Depleted Kanał Mode zuboŝany n-type Transistor typu n I DS I DS U GS U DS I DS U GS I DS Depleted Kanał Mode zuboŝany p-type Transistor typu p U DS

53 IFE, B&T, V semester 53 CMOS Inverter

54 IFE, B&T, V semester 54 CMOS inverter cross-section Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well.

55 IFE, B&T, V semester 55 CMOS inverter scheme

56 IFE, B&T, V semester 56 CMOS inverter and pair of switches Note: switches must operate in a complementary fashion.

57 IFE, B&T, V semester 57 CMOS inverter operation v 1 is high circuit with v1 = VDD (logic-1 level, or VOH); equivalent circuit. graphical construction to determine the operating point

58 IFE, B&T, V semester 58 CMOS inverter operation v 1 is low circuit with v1 = 0V (logic-0 level, or V OL ); equivalent circuit. graphical construction to determine the operating point

59 IFE, B&T, V semester 59 Voltage transfer characteristic of the CMOS inverter

60 IFE, B&T, V semester 60 Dynamic operation of a capacitive loaded CMOS inverter equivalent circuit during the capacitor discharge.

61 IFE, B&T, V semester 61 Dynamic operation of a capacitive loaded CMOS inverter input and output waveforms trajectory of the operating point as the input goes high and C discharges through the Q N