Chapter 10 BINARY ARITHMETIC, DECODING AND MUX LOGIC UNITS
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1 Chapter 10 BINARY ARITHMETIC, DECODING AND MUX LOGIC UNITS
2 Lesson 5 Multiplexer Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
3 Outline Multiplexer 2 of 1 and 4 of 1 line multiplexer 8 of 1 4 of 16 line multiplexer Multiplexers Arranged as tree Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
4 Multiplexer A circuit that sends the binary information from one of the input line to the output and that line is selected as per the address or channel select bits. A circuit that selects the input line among the input lines as per channel-selector logicinputs and gives that line input at the output. A multiplexer selects a unique input line according to the address or channel selector inputs to it Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
5 Multiplexer Applications Sharing the Boolean function circuit outputs, ports, devices and resources Logic Design of circuits Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
6 n to 1 Multiplexer A circuit, which takes the 2 n -input line but presumes with only one = active and gives that at output Selection is using n-address (channel) select bits Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
7 Outline Multiplexer 2 of 1 and 4 of 1 line multiplexers 8 of 1line multiplexer 4 of 16 line multiplexer Multiplexers Arranged as tree Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
8 2-channel input-selector (2 to 1 multiplexer) One channel selector pin A (= 0 for channel or Boolean function F and = 1 0 for channel F ) 1 Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
9 Multiplexer as Line Selector Assume that we have two logic circuits that provide the outputs. One is for a logic function F and other is for F. 0 1 We have to select only one by giving appropriate instruction at the pins called address pin or channel select pin A. A multiplexer will select for the output only one of F or F 0 1 Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
10 2 of 1 Multiplexer Inputs Select Input Output I0 I1 A Y F0 F1 0 F0 F0 F1 1 F 1 F1 F0 I1 I0 F0 or F1 A Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
11 4 of 1 Multiplexer Inputs Select Input I0 I1 I2 I3 A1 A0 Output F0 F1 F2 F3 0 0 F0 F0 F1 F2 F3 0 1 F1 F0 F1 F2 F3 1 0 F2 F0 F1 F2 F3 1 1 F3 Y Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
12 4 of 1 Multiplexer F3 I3 F2 I2 F0 or F1 or F1 I1 Y F2 or F3 F0 I0 A1 A0 Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
13 Outline Multiplexer 2 of 1 and 4 of 1 line multiplexers 8 of 1 line multiplexer 4 of 16 line multiplexer Multiplexers Arranged as tree Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
14 Inputs 8 of 1 Multiplexer Select Inputs Output I7... I0 000 I0 I7... I0 001 I1 I7... I0.... I7... I0 111 Y0 I7 Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
15 F7 F6 F5 F4 F3 F2 F1 F0 I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0 8 of 1 Multiplexer Y F0 or F1 or F2 or F3 Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
16 Outline Multiplexer 2 of 1 and 4 of 1 line multiplexers 8 of 1 line multiplexer 4 line of 16 line multiplexer Multiplexers Arranged as tree Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
17 16 of 1 (16 line to 4line) Multiplexer with one input and one output control (enabling/disabling) pin G A15. A1 A0.. Y G = 0 enables the output Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
18 16 of 1 (8 line to 3 line) Multiplexer with one output control (enabling/disabling) pin OE A15. A0.. A2 A1 A0 Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education, Y OE = 0 means enable the input
19 Outline Multiplexer 2 of 1 and 4 of 1 line multiplexers 8 of 1 line multiplexer 4 of 16 line multiplexer Multiplexers Arranged as tree Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
20 Tree We get the (m of 1) multiplexing from i numbers of the (m of 1) multiplexers when the multiplexers arranged as a tree Here m = i.m where i is an integer and m = 2 n where n is the number of channel selector lines at each of the i multiplexers Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
21 A3A2A1A0 I0. I3 I4.. I7 I8.. I11 Multiplexer Tree Y F0 or.. or F15 I12.. I15 Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
22 Summary Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
23 Multiplexer A multiplexer provides output path (channel) for the one channel data from the number of channels at a given instant. Its important application is in sharing the circuits, ports, devices and resources. A number of multiplexers can be arranged in tree topology to obtain a bigger numbers of channel-multiplexer A multiplexer has control gate pin(s) for output enable Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
24 End of Lesson 5 on Multiplexer Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
25 THANK YOU Ch10L5-"Digital Principles and Design", Raj Kamal, Pearson Education,
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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS