10.3 CMOS Logic Gate Circuits
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1 11/14/2004 section 10_3 CMOS Logic Gate Circuits blank.doc 1/ CMOS Logic Gate Circuits Reading ssignment: pp Q: Can t we build a more complex digital device than a simple digital inverter? : HO: CMOS Device Structure Q: : HO: Synthesis of CMOS Gates HO: Examples of CMOS Logic Gates Example: CMOS Logic Gate Synthesis Example: nother CMOS Logic Gate Synthesis
2 11/14/2004 CMOS Device Structure.doc 1/4 CMOS Device Structure For every CMOS device, there are essentially two separate circuits: 1) The Pull-Up Network 2) The Pull-Down Network The basic CMOS structure is: V DD C PUN D Inputs Y = f (,,C,D) C D PDN Output CMOS logic gate must be in one of two states!
3 11/14/2004 CMOS Device Structure.doc 2/4 State 1: PUN is open and PDN is conducting. V DD PUN PDN Y =0 In this state, the output is LOW (i.e., Y =0). State 2: PUN is conducting and PDN is open. V DD PUN Y =0 In this state, the output is HIGH (i.e.,y =1). PDN
4 11/14/2004 CMOS Device Structure.doc 3/4 Thus, the PUN and the PDN essentially act as switches, connecting the output to either V DD or to ground: V DD V DD Y =0 OR Y =V DD * Note that the key to proper operation is that one switch must be closed, while the other must be open. * oth switches closed or both switches open would cause an ambiguous digital output! * To prevent this from occurring, the PDN and PUN must be complementary circuits.
5 11/14/2004 CMOS Device Structure.doc 4/4 For example, consider the CMOS inverter: V DD PUN Y = PDN For more complex digital CMOS gates (e.g., a 4-input OR gate), we find: 1) The PUN will consist of multiple inputs, therefore requires a circuit with multiple PMOS transistors. 2) The PDN will consist of multiple inputs, therefore requires a circuit with multiple NMOS transistors.
6 11/14/2004 Synthesis of CMOS Gates.doc 1/4 Synthesis of CMOS Gates Let s consider the design synthesis of CMOS gates by considering the design synthesis of PUN and PDN separately. PDN Design Synthesis 1. If the PDN is conducting, then the output will be low. Thus, we must find a oolean expression for the complemented output Y. In turn, the PDN can only be conducting if one or more of the NMOS devices are conducting and NMOS devices will be conducting (i.e., triode mode) when the inputs are high (V GSN =V DD ). Thus, we must express Y in terms of un-complemented inputs Y = f,,c ).,, C, etc (i.e., ( ) e.g., Y = + C This step may test our oolean algebraic skills!
7 11/14/2004 Synthesis of CMOS Gates.doc 2/4 2. Then, we realize ND operations in Y f (,,C ) series NMOS devices. E.G.: = with Y PDN Note that Y =0 if both = V DD ND = V DD. Y = 3. Likewise, we realize OR operations with parallel NMOS devices. E.G.: Y Note that Y =0 if either = V DD OR = V DD. Y = + PDN
8 11/14/2004 Synthesis of CMOS Gates.doc 3/4 PUN Design Synthesis 1. If the PUN is conducting, then the output will be high. Thus, we must find a oolean expression for the uncomplemented output Y. In turn, the PUN can only be conducting if one or more of the PMOS devices are conducting and PMOS devices will be conducting (i.e., triode mode) when the inputs are low (V GSP = -V DD ). Thus, we must express Y in terms of complemented inputs Y = f,,c ).,, C, etc (i.e., ( ) e.g., Y = + C This step may test our oolean algebraic skills!
9 11/14/2004 Synthesis of CMOS Gates.doc 4/4 2. Then, we realize ND operations with series PMOS devices. E.G.: V DD PUN Note that Y =V DD if both = 0 ND = 0. Y = Y 3. Likewise, we realize OR operations with parallel PMOS devices. E.G.: V DD Note that Y = V DD if either = 0 OR =0. PUN Y = + Y
10 11/14/2004 Examples of CMOS Logic Gates.doc 1/3 Examples of CMOS Logic Gates See if you can determine the oolean expression that describes these pull-down networks: See now if you can determine the oolean algebraic expression for these pull-up networks:
11 11/14/2004 Examples of CMOS Logic Gates.doc 2/3 Now, we will make a simplifying change of symbols: Effectively, these symbols represent the fact that we are now considering MOSFETs as switches, which can be placed either in an open state or a conducting state. Note there are two kinds of switches the ones that conduct when the input is high (i.e., NMOS) and ones that conduct when the input is low (i.e., PMOS).
12 11/14/2004 Examples of CMOS Logic Gates.doc 3/3 nd now consider these logic gates: Note the PUN and the PDN for each of these circuits have equivalent oolean expressions (make sure you see this!).
13 11/14/2004 Example CMOS Logic Gate Synthesis.doc 1/6 Example: CMOS Logic Gate Synthesis Problem: Design a CMOS digital circuit that realizes the oolean function: Y = + + C Solution: Follow the steps of the design synthesis handout! Step1: Design the PDN First, we must rewrite the oolean function as: ( ) Y = f,,c In other words, write the complemented output in terms of un-complemented inputs. Time to recall our oolean algebra skills!
14 11/14/2004 Example CMOS Logic Gate Synthesis.doc 2/6 We must first complement this equation, and then apply DeMorgan s Theorem (several times!). Y = + + C Y = + + C ( )( C ) ( )( C ) = + Logically, this result says: = + + ( )( C ) = + + = + C + + C ( ) = + + C + C = + C Y is low if is high, OR if both ND C are high. We can thus realize this logic with the following NMOS PDN:
15 11/14/2004 Example CMOS Logic Gate Synthesis.doc 3/6 Y PDN C Y = + C Step2: Design the PUN First, we must rewrite the oolean function as: ( ) Y = f,,c In other words, write the un-complemented output in terms of complemented inputs.
16 11/14/2004 Example CMOS Logic Gate Synthesis.doc 4/6 gain, using DeMorgan s Theorem: Logically, this result says: Y = + + C = + C ( C ) = + Y is high if is low ND either OR C are low. We can thus realize this logic with the following PMOS PUN:
17 11/14/2004 Example CMOS Logic Gate Synthesis.doc 5/6 V DD C PUN Y = ( + C ) Y Thus, the entire CMOS realization is:
18 11/14/2004 Example CMOS Logic Gate Synthesis.doc 6/6 V DD C Y = + + C C
19 11/14/2004 Example nother CMOS Logic Gate Synthesis.doc 1/4 Example: nother CMOS Logic Gate Synthesis Now let s design a gate that realizes this oolean algebraic expression: Step 1: Design PDN Y = ( + ) C First, let s rewrite oolean expression as Y f (,,C) ( ) ( ) Y = + C Y = + C ( ) Y = + + C Y = + C = : Q: Yikes! We cannot write this expression explicitly in terms of uncomplemented inputs,, and C! The input C appears as C in the expression. What do we do now? : n easy problem to solve! We can essentially make a substitution of variables: C = C
20 11/14/2004 Example nother CMOS Logic Gate Synthesis.doc 2/4 nd thus: Y = + C Therefore, the inputs to this logic gate should be,, and C (i.e,,, and the complement of C ). Note that this oolean expression says that: The ouput is low if either, ND are both high, OR C is high Of course another way of saying this is: The output is low if either ND are both high, OR C is low The PDN is therefore: Y Y = + C = + C C = C
21 11/14/2004 Example nother CMOS Logic Gate Synthesis.doc 3/4 Step 2: Design the PUN Note we have as similar problem as before the expression for Y cannot explicitly be written in terms of complemented inputs and C,, : Y = ( + ) C Note we can again solve this problem by using the same substitution of variable C: C = C C = C Therefore: ( ) ( ) Y = + C = + C This expression says that: The output will be high if, either OR are low, ND C is low Which is equivalent to saying: The output will be high if, either OR are low, ND C is high The CMOS digital logic device is therefore:
22 11/14/2004 Example nother CMOS Logic Gate Synthesis.doc 4/4 V DD C = C Y ( ) ( ) ( ) Y = + C = + C = + C C = C
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