NCP5359A. Gate Driver for Notebook Power Systems

Transcription

1 Gate Driver for Notebook Power Systems The NP5359A is a high performance dual MOSFET gate driver optimized to drive the gates of both high side and low side power MOSFETs in a synchronous buck converter. Each of the drivers can drive up to 3 nf load with a 25 ns propagation delay and 5 ns transition time. Adaptive nonoverlap and power saving operation circuit can provide a low switching loss and high efficiency solution for notebook and desktop systems. A high floating top driver design can accommodate VBST voltage as high as 35 V, with transient voltages as high as 35 V. Bidirectional pin can provide a fault signal to controller when the gate driver fault detect under OVP, UVLO occur. Also, an undervoltage lockout function guarantees the outputs are low when supply voltage is low, and a thermal shutdown function provides the I with overtemperature protection. Features Faster Rise and Fall Times Thermal Shutdown Protection Adaptive Nonoverlap ircuit Floating Top Driver Accommodates Boost Voltages of up to 30 V Output Disable ontrol Turns Off Both MOSFETs omplies with VRM. Specifications Undervoltage Lockout Power Saving Operation Under Light Load onditions Thermally Enhanced Package These are Pb Free Devices Typical Applications Power Solutions for Desktop and Notebook Systems 8 PIN ONNETIONS BST V BST V D SUFFIX ASE 75 A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package 8 8 MARKING DIAGRAMS DRVH 5359A ALYW MN SUFFIX ASE 506AA 4 AA = Device ode M = Date ode = Pb Free Package 8 AA M DRVH (Top View) ORDERING INFORMATION Device Package Shipping NP5359ADR2G NP5359AMNR2G NP5359AMNTBG (Pb Free) (Pb Free) (Pb Free) 2500 Tape & Reel 3000 Tape & Reel 3000 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD80/D. Semiconductor omponents Industries, LL, 2009 September, 2009 Rev. Publication Order Number: NP5359A/D

2 BST V Fault hip Level Shift and Driver DRVH DRVH omparator > 2.2 V =, Else = 0 Falling Edge Delay UVLO Fault.0 V l Thermal Shutdown hip mv F omparator 0.8 V < < 2.2 V =, Else 0 l R Q S Q Pre Over voltage Pre OV Falling Edge Delay hip V 2 V/ V l Driver Pre OV Figure. Internal Block Diagram 2

3 4 V to 5 V BST DRVH VOUT 0 V to 3.2 V V Figure 2. Typical Application PIN DESRIPTION Symbol Description BST Upper MOSFET Floating Bootstrap Supply Pin 2 2 Input Pin When voltage is higher than 2.2 V, DRVH will set to and set to 0 When voltage is lower than 0.8 V, will set to and DRVH set to 0 When 0.8 V < < 2.2 V and < 0, will set to When 0.8 V < < 2.2 V and > 0, will set to Enable Pin When OVP, TSD or UVLO has happened, the gate driver will pull the pin to low 4 4 V onnect to Input Power Supply 0 V to 3.2 V 5 5 Low Side Gate Drive Output 6 6 Ground Pin 7 7 Switch Node Pin 8 8 DRVH High Side Gate Drive Output 3

4 MAXIMUM RATINGS Thermal haracteristics, Plastic Package Thermal Resistance Junction to Air Rating Symbol Value Unit (20.2 sq mm, 2 oz u) R JA Operating Junction Temperature Range T J 0 to 50 Operating Ambient Temperature Range T A 0 to 85 Storage Temperature Range T stg 55 to 50 Moisture Sensitivity Level MSL Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditions is not implied. Extended exposure to stresses above the Recommended Operating onditions may affect device reliability. MAXIMUM RATINGS Pin Symbol Pin Name V MAX V MIN Vcc Main Supply Voltage Input 5 V 0.3 V /W BST Bootstrap Supply voltage 35 V wrt / 40 V 50 ns wrt / 5 V wrt / 0.3 V wrt / Switching Node (Bootstrap Supply Return) 35 V wrt / 40 V 50 ns wrt / DRVH High Side Driver Output BST 0.3 V 35 V 50 ns wrt / 5 V wrt / VD 0 V (200 ns) 0.3 V wrt / 2 V (200 ns) wrt / Low Side Driver Output Vcc 0.3 V 0.3 V 5 V (200 ns) DRVH and ontrol Input 6 V 0.3 V Enable Pin 6 V 0.3 V Ground 0 V 0 V. Latchup urrent Maximum Rating: 00 ma per JEDE standard: JESD Moisture Sensitivity Level (MSL): &3 per IP/JEDE standard: J STD 020A. 3. The maximum package power dissipation limit must not be exceeded. TJ(max) TA PD R JA NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. 4

5 ELETRIAL HARATERISTIS (V = 0 V 3.2 V, T A = 0 to 85, V = 5 V unless otherwise noted) haracteristics Symbol Test onditions Min Typ Max Units Supply Voltage V Operating Voltage V V Power ON Reset threshold V POR 2.8 V Supply urrent V Quiescent Supply urrent in Normal I V_NORM = 5 V, = OS, F = 00 k ma Operation LOAD = 0 p V Standby urrent I V_SB = ; No switching ma BST Quiescent Supply urrent in Normal I BST_normal = 5 V, = 0 V.0.8 ma Operation I BST2_normal =, = 0 V.0.8 BST Standby urrent I BST_SD = 5 V 0.25 ma I BST2_SD = 0.25 Undervoltage Lockout V Start Threshold V TH V V UVLO Hysteresis V HYS.0 V Output Overvoltage Trip Threshold at Startup OVPSU Power Startup time, V > 9 V. (Without trimming) V Input Input Voltage High V _HI 2.0 V Input Voltage Low V _LOW.0 V Hysteresis (Note 4) V _HYS 500 mv Enable Pin Sink urrent I _SINK V = 5.5 V 4.0 ma Propagation Delay Time (Note 4) tpd h ns tpd l ns Input DRVH omparator Drop Threshold VTH_DRVH 2.2 V Input Self Bias Voltage V V omparator Rise Threshold VTH_ 0.8 V Input urrent I = 0 V, = 30 A High Side Driver Output Resistance, Sourcing R H_TG V BST V = 2 V Output Resistance, Sinking R L_TG V BST V = 2 V Output Resistance, unbiased (Note 4) BST = 0 V 0 55 k Pull Down Resistance (Note 4) to 0 55 k Transition Time (Note 6) tr DRVH LOAD = 3 nf, V BST V = 2 V 6 25 ns tf DRVH LOAD = 3 nf, V BST V = 2 V 5 20 Propagation Delay (Notes 4 & 5) tpdh DRVH Driving High, LOAD = 3 nf 0 35 ns tpdl DRVH Driving Low, LOAD = 3 nf 5 30 Low Side Driver Output Resistance, Sourcing R H_BG = Output Resistance, Sinking R L_BG = V Output Resistance, unbiased (Note 4) BST = 0 V 0 55 k Transition Time (Note 6) tr LOAD = 3 nf 6 25 ns tf LOAD = 3 nf 5 20 Propagation Delay (Notes 4 & 5) tpdh Driving High, LOAD = 3 nf 0 35 ns tpdl Driving Low, LOAD = 3 nf 5 35 Negative urrent Detector Threshold V NDT (Note 6).0 mv Thermal Shutdown Thermal Shutdown Tsd (Note 6) Thermal Shutdown Hysteresis Tsd hys (Note 6) Guaranteed by design; not tested in production. 5. For propagation delays, t pdh refers to the specified signal going high t pdl refers to it going low. 6. Design guaranteed. 5

6 Table. DEODER TRUTH TABLE Input ZD DRVH Greater than 2.2 V X Low High Greater than 0.8 V, but less than 2.2 V High (current through MOSFET is greater than 0) High Low Greater than 0.8 V, but less than 2.2 V Low (current through MOSFET is less than 0) Low Low Less than 0.8 V X High Low tpdl t f 90% 2 V 0% 0% 90% tpdh DRVH t rdrvh tpdl DRVH t fdrvh 90% 90% t r DRVH 0% 2 V 0% tpdh Figure 3. DRVH IL Figure 4. Timing Diagram 6

7 APPLIATION INFORMATION The NP5359A gate driver is a single phase MOSFET driver designed for driving two N channel MOSFETs in a synchronous buck converter topology. This driver is compatible with the NP348B gate drive. This gate drives operation is similar with the NP348B, but has two additional new features: Bidirection fault detection and multilevel input. When the gate driver works with ON Semiconductor s NP5392 controller, it can provide a difference output logic status through multi level input. For this new feature, higher efficiency can be provided. For the bidirection fault detection function, it is used to provide a driver state information to other gate drivers and controller in a multiphase buck converter. e.g overvoltage protection (OVP) function at startup, thermal shutdown and undervoltage lockout (UVLO). This feature can provide an additional protection function for the multi phase system when the fault condition occurs in one channel. With this additional feature, converter overall system will be more reliable and safe. Enable Pin The bidirection enable pin is connected with an open drain MOSFET. This pin is controlled by internal or external signal. There are three conditions will be triggered:. The voltage at N pin is higher than preset voltage at power startup. 2. The controller hits the UVLO at V pin. 3. The controller hits the thermal shutdown. When the internal fault has been detected, pin will be pull low. In this case, the drive output DRVH and will be forced low, until the fault mode remove then restart automatic. Undervoltage Lockout The DRVH and are held low until V reaches 9 V during startup. The signals will control the gate status when V threshold is exceeded. If V decreases to 3.2 V below the threshold, the output gate will be forced low until input voltage V rises above the startup threshold. Power ON reset Power on reset feature is used to protect a gate driver avoid abnormal status driving the startup condition. When the initial soft start voltage is higher than 3.2 V, the gate driver will monitor the switching node pin. If pin high than.9 V, bottom gate will be force to high for discharge the output capacitor. The fault mode will be latch and pin will force to be low, unless the driver is recycle. When input voltage is higher than 9 V, the gate driver will normal operation, top gate driver DRVH and bottom gate driver will follow the signal decode to a status. Adaptive Nonoverlap The nonoverlap dead time control is used to avoid the shoot through damage the power MOSFETs. When the signal pull high, will go low after a propagation delay, the controller will monitors the switching node (N) pin voltage and the gate voltage of the MOSFET to know the status of the MOSFET. When the low side MOSFET status is off an internal timer will delay turn on of the high side MOSFET. When the pull low, gate DRVH will go low after the propagation delay (tpd DRVH). The time to turn off the high side MOSFET is depending on the total gate charge of the high side MOSFET. A timer will be triggered once the high side MOSFET is turn off to delay the turn on the low side MOSFET. Layout Guidelines Layout is very important thing for design a D D converter. Bootstrap capacitor and V capacitor are most critical items, it should be placed as close as to the driver I. Another item is using a plane. Ground plane can provide a good return path for gate drives for reducing the ground noise. Therefore pin should be directly connected to the ground plane and close to the low side MOSFET source pin. Also, the gate drive trace should be considered. The gate drives has a high di/dt when switching, therefore a minimized gate drives trace can reduce the di/dv, raise and fall time for reduce the switching loss. 7

8 PAKAGE DIMSIONS ASE ISSUE AJ Y B X 8 A 5 4 S 0.25 (0.00) M Y M K NOTES:. DIMSIONING AND TOLERANING PER ANSI Y4.5M, ONTROLLING DIMSION: MILLIMETER. 3. DIMSION A AND B DO NOT INLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXESS OF THE D DIMSION AT MAXIMUM MATERIAL ONDITION THRU ARE OBSOLETE. NEW STANDARD IS Z H G D 0.25 (0.00) M Z Y S X S SEATING PLANE 0.0 (0.004) N X 45 M J MILLIMETERS INHES DIM MIN MAX MIN MAX A B D G.27 BS BS H J K M N S SOLDERING FOOTPRINT* SALE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 8

9 PAKAGE DIMSIONS MN SUFFIX ASE 506AA 0 ISSUE D PIN ONE REFERE D A B NOTES:. DIMSIONING AND TOLERANING PER ASME Y4.5M, ONTROLLING DIMSION: MILLIMETERS. 3. DIMSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWE 0.25 AND 0.30 MM FROM TERMINAL. 4. OPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 2 X X 0.0 ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ TOP VIEW E MILLIMETERS DIM MIN MAX A A A REF b D 2.00 BS D E 2.00 BS E e 0.50 BS K 0.20 L A 8 X SEATING PLANE 0.08 A SIDE VIEW (A3) D2 e/2 4 8 X L e E2 K X b A B NOTE 3 BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMT: Literature Distribution enter for ON Semiconductor P.O. Box 563, Denver, olorado 8027 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NP5359A/D