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1 Chapter 9 xercise 9. (a) Implement a output (ecimal) ecoer for -out-of- coe using NAND gates. The -out-of- coe represents ecimal igits as shown in the following table: i x x x x x 8 9 ach output z i of the ecoer is activate when the input has the -out-of- coe that represents the value i in ecimal an the enable input =. The expressions for the outputs are: z = x x x x x z = x x x x x z = x x x x x z = x x x x x z = x x x x x z = x x x x x z = x x x x x z = x x x x x z 8 = x x x x x z 9 = x x x x x Part of the gate network for the circuit is shown in Figure 9.. x x x x x x x x x x x x x x x x x x x x z z Figure 9.: Network for xercise 9. (a)

2 Solutions Manual - Introuction to Digital Design - March, 999 (b) Implement a output (ecimal) ecoer using NAND gates for a -bit Gray coe. The coe table is shown next. The expressions for the ten outputs z to z 9 are: i g g g g 8 9 z = g g g z = g g g z = g g g z = g g g z = g g g z = g g g z = g g g g z = g g g g z 8 = g g z 9 = g g The implementation, shown in Figure 9., consists of six -input NAND gates, two -input NAND gates, two -input NAND gates, an NOT gates. (c) Implement a output (ecimal) ecoer using NAND gates for a --- coe. The coe table is shown next. i c c c c 8 9 The switching expressions for the ecoer outputs are: z = c c c c

3 Solutions Manual - Introuction to Digital Design - March, 999 g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g z z z z z z z g g g g z g g z8 g g z9 Figure 9.: Network for xercise 9. (b) z = c c c c z = c c c c z = c c c c z = c c c c z = c c c c z = c c c c z = c c c c z 8 = c c c c z 9 = c c c c Part of the gate network that implements these expressions is shown in Figure 9..

4 Solutions Manual - Introuction to Digital Design - March, 999 c c c c c c c c c c c c c c c c z z Figure 9.: Gate network for xercise 9. (c) xercise 9.: Implement a BCD ecoer using an xcess- ecoer, a -input binary ecoer an a NOR gate. The relation between BCD coe an the xcess- coe is: x 8 9 z (x-) y (BCD) where x is the raix- representation of the input vector an z an y are the inices of the outputs of the ecoers with value. From the table we see that for x between an 9, the output of the xcess- ecoer can be relabele to give some of the outputs of the BCD ecoer. Since for x between an, no output of the xcess- ecoer has value, it is necessary to ecoe these values separately. It's possible to o this using a -input binary ecoer that has as inputs the bits x an x (the least signicant bits) an making the enable input active when x. The corresponing network is shown in Figure 9., on page. xercise 9. The -bit O/ven parity functions have value when the number of s in the input vector is o/even. The implementation of these functions using a -input ecoer an OR gates is shown in Figure 9.. The even parity is prouce by output P an the o parity by output OP. xercise 9.: For a coincient ecoer using n =an k =,we use r = n=k =-input ecoers an -input AND gates. The circuit is shown in Figure 9.. In the gure only some of the AND gates are shown, with the corresponing output numbers. In general, if we partition the input into groups of bits, we get: u = 8x +x +x 9 + x 8 s = 8x +x +x + x t = 8x +x +x + x an the output z i =ifi = u 8 + s + t.

5 Solutions Manual - Introuction to Digital Design - March, 999 x x x x xcess- ec 8 9 y y y y y8 y9 BCD: (x,x,x,x) ecoe outputs: yi ec y y y y Figure 9.: BCD ecoer - xercise 9. xercise 9. Part (a) number of levels in the tree of ecoers = = = levels. the number of ecoers in this tree = = 99 ecoers. Part (b) using coincient ecoing we nee ve -input ecoers to receive the inputs. We woul nee AND gates. xercise 9. Let us call x =(x 9 ;x 8 ;x ;x ;x ;x ;x ;x ;x ;x ) the input vector of the -input ecoer. The output vector will epen on the coe to be generate. x x x x Dec. 8 9 I I I I I I I I I8 I9 I I I I I I I I I I8 I I I I I I I I I9 I I I OP P Figure 9.: Parity functions - xercise 9.

6 8 Solutions Manual - Introuction to Digital Design - March, 999 x x x9 x8 x x x x x x x x Decoer Decoer Decoer z9 z9 z z z Figure 9.: Coincient ecoer for xercise 9. (a) For the -out-of- coe (consier the table presente in exercise 9.) the expressions are: z = (x + x + x + x ) z = (x + x + x + x 8 ) z = (x + x + x + x 9 ) z = (x + x + x + x ) z = (x + x + x 8 + x 9 ) (b) For the -bit Gray coe the output vector is (z ;z ;z ;z ) (see table in xercise 9..). The expressions are: z = (x 8 + x 9 ) z = (x + x + x + x + x 8 + x 9 ) z = (x + x + x + x ) z = (x + x + x + x + x 9 ) (c) For xcess- coe the output vector is (z ;z ;z ;z ). The xcess- coe is shown in the next table: i z z z z 8 9

7 Solutions Manual - Introuction to Digital Design - March, The expressions for the outputs are: z =(x + x + x + x 8 + x 9 ) z =(x + x + x + x + x 9 ) z =(x + x + x + x + x 8 ) z =(x + x + x + x + x 8 ) The networks of gates are easily obtaine from these expressions. xercise 9. From the gure, we get the following expressions for the circuit outputs: D = (I 8 + I 9) = I 8 I 9 C = ((I 8 + I 9) :(I + I + I + I )) = (I 8 I 9 :(I + I + I + I )) B = (I 8 I 9 :(I I I + I I I + I + I )) = (I 8 I 9 (I + I )+I 9 I 8 I I I I (I + I )) A = ((I 8 I 9 ):(I I I I + I I I + I I + I )+I 9) = (I 9 + I 9 I 8 I + I 9 I 8 I I I + I 9 I 8 I I I I I + I 9 I 8 I I I I I I I ) From these expression we get the following table: I9 I8 I I I I I I I D' C' B' A' Output(ecimal) Consequently, ifz =(D ;C ;B ;A ) represents a ecimal igit z in BCD, we get ( i if (I i z = = for some i>) an (I = for all j>i); j otherwise which correspons to a priority encoer function.

8 Solutions Manual - Introuction to Digital Design - March, 999 xercise 9.8: (a) From Figure 9. of the textbook we get the following table: BCD -segment isplay b b b b abcefg The implementation of this coe converter using a ecoer an OR gates is shown in Figure 9.. The implementation using a ecoer an an encoer is not ecient, an for this reason it is not shown. Two -bit encoers or a large -bit encoer shoul be use, an since there is only a small set of -segment coes, many of the encoer inputs woul not be use, or woul require OR gates to combine two or more ecoer outputs. b b b b ecoer 8 9 a b c e f g Figure 9.: Network of xercise 9.8 (a)

9 Solutions Manual - Introuction to Digital Design - March, 999 (b) Four-bit binary to -bit Gray coe. The function table is: binary Gray b b b b g g g g Although the implementation by a gate network is quite simple, we show two ierent implementations in Figure 9.8. One uses a ecoer an OR gates, an the other uses a ecoer an encoer. b b b b ecoer 8 9 g g g g b b b b ecoer encoer g g g g Figure 9.8: to Gray-coe converter - xercise 9.8 (b)

10 Solutions Manual - Introuction to Digital Design - March, 999 (c) BCD to -out-of- coe converter. The function table of the system follows: BCD -out-of- b b b b c c c c c Two implementations of this coe converter, one using a ecoer an OR gates, an another using a ecoer an encoer are shown in Figure 9.9. b b b b ecoer 8 9 c c c c c b b b b ecoer encoer c c c c c Figure 9.9: Network of xercise 9.8 (c) xercise 9.9: The implementation is shown in Figure 9., on page. The outputs of the ecoer are labele accoring to the Gray coe an connecte to the corresponing inputs of the encoer. xercise 9. A specication of the cyclic priority encoer is z = i if x i = an x (i+j)mo 8 = for (j (c, i) mo 8)

11 Solutions Manual - Introuction to Digital Design - March, 999 g g g ecoer ncoer b b b Figure 9.: Coe converter -Gray, xercise 9.9 where c is the value of the control input. In one implementation, a left -shifter is use to move the highest-priority input (x c ) to the highest input of the priority encoer (w ). The amount of shift is therefore, c to the left (this is obtaine by complementing each bit of the binary representation of c). This prouces w (i+,c)mo 8 = x i, so that if x i is the highest-priority input, the output of the priority encoer woul be (i +, c) mo 8. Consequently, to obtain the correct result, the output of the encoer y has to be ecremente by (, c) mo8. That is, z = (y, (, c)) mo 8 = (y + c +)mo 8 The corresponing network is shown in Figure 9.(a). To avoi the complementation of c, we can use a right shift of c instea of the left shift. This woul put x c in w instea of w. Therefore, the connections between the output of the shifter an the input of the priority encoer have to be as shown in the Figure 9.(b). c x x x x x x x x x x x x x x x - - Left - -Shifter - w w A Priority ncoer A cin + z z z x x x x x x x x x x x x x x x Right -Shifter 8 9 A Priority ncoer c c c c c (a) (b) Figure 9.: Cyclic priority encoer - xercise 9.

12 Solutions Manual - Introuction to Digital Design - March, 999 xercise 9. Input: x f; ; ; ; ; ; ; g, represente in binary by the vector x = fx ;x ;x g;x i f; g. Output: y f; ; ; ; ; ; ; g, represente in binary by the vector y = fy ;y ;y g;y i f; g Function: y =(x) mo8 The function table for the system is: x y The implementation of this system using a binary ecoer an a binary encoer is shown in Figure 9.. x x x ecoer ncoer y y y Figure 9.: Function y = x using ecoer an encoer xercise 9. The -input encoer network in Figure 9. of the textbook consists of two levels of moules. In the rst level there are eight encoers, each of them encoing part of the input vector x. Since there is only one input with value, the outputs of all encoer moules are except the one corresponing to this x i =. Also, only the corresponing A has value. Naming w j the value of the -bit output of the encoer that has inputs x i, 8k i 8k +, the output is escribe as: an w j =( i mo 8 if xi = for j = bi=8c otherwise A j = ( if xi = for j = bi=8c otherwise In the secon level, there are three OR gates with eight inputs each which prouce (y ;y ;y ) an an eight-input encoer to encoe the A outputs of the rst level encoers an prouce (y ;y ;y ). The connection of the OR gates prouces: X j= y j j = OR(w ;w ; :::; w )=i mo 8

13 Solutions Manual - Introuction to Digital Design - March, 999 since all w's except one are. Similarly, the output of the secon-level encoer is an, therefore, y = X j= X j= an the network performs the encoing function. y j j = bi=8c y j j = bi=8c + i mo 8 = i xercise 9. The -input multiplexer has eight select inputs. Since each -input multiplexer has two select inputs, the tree has four levels. The number of multiplexer in each level is: rst level: = secon level: = thir level: = (9:) fourth level: = A total of 8 multiplexers istribute in four levels are require to implement a -input multiplexer. xercise 9. The exercise asks for a multiplexer tree with r levels, an n inputs in the last level, with n = rk. That means, each multiplexer has k selection lines an k inputs. Figure 9. shows a block iagram of the rst an secon level of the tree. We can see from the gure that from one level to the next, the number of inputs is multiplie by p = k (the number of inputs of each iniviual multiplexer moule). For r levels, the total number of inputs in the last level is p r = rk = n. Mux Mux Mux Mux Level p inputs p inputs Level The number of moules is: Figure 9.: Two levels of multiplexer tree r, X j= p j = p + p + p + :::+ p r, = pr, p,

14 Solutions Manual - Introuction to Digital Design - March, 999 xercise 9. f(a; b; c; ) =oneset(; ; ; 9; ; ) abc f(a; b; c; ) 8 9 (a) the implementation using 8-input multiplexer is presente in Figure 9.. The expression can be manipulate as follows: f(a; b; c; ) =a b c + a b c + a bc + ab c + abc + abc f(a; b; c; ) =m (a; b; c) + m (a; b; c) + m (a; b; c) + m (a; b; c) + m (a; b; c)( + ) MUX f(a,b,c,) a b c Figure 9.: Implementation for xercise 9. (a)

15 Solutions Manual - Introuction to Digital Design - March, 999 (b) the implementation using -input multiplexer is presente in Figure 9.. The expression for this implementation is: f(a; b; c; ) =m (a; b)(c + c)+m (a; b)c + m (a; b)c + m (a; b)(c + c ) f(a; b; c; ) =m (a; b) + m (a; b)(c + ) + m (a; b)(c + ) + m (a; b)c c MUX f(a,b,c,) c a b Figure 9.: Network for xercise 9. (b) xercise 9. The implementation of an 8-input multiplexer using a -input binary ecoer an NAND gates is shown in Figure 9.. The selection lines s =(s ;s ;s ) are ecoe an use to make z = i j, such that j = s = s : + s :+s. i i s s s ecoer i i i z i i i Figure 9.: Network for xercise 9.

16 8 Solutions Manual - Introuction to Digital Design - March, 999 xercise 9. Part (a) The specication of an n,bit simple shifter is given on page of the textbook. A escription of an 8-bit shifter is easily obtaine from there. The block iagram of the circuit is shown in Figure 9.. x 8 x x x x x x x x x - s shift/no shift left/right SHIFTR y y y y y y y y Figure 9.: Block iagram of 8-bits shifter To generate each output, a -input multiplexer is use as shown in Figure 9.8. The selection inputs are ene accoring to following table: c c Operation s LFT shift L RIGHT shift R NO SHIFT no shift - DISABLD - - Consiering shift = L = an no shift = R = (same convention use in page of the textbook) we obtain the following Kmaps: x i- x i x i+ MUX y i c c Figure 9.8: Circuit for each output of the 8-bit simple shifter s s c c

17 Solutions Manual - Introuction to Digital Design - March, that correspon to the following expressions: c = + s c = s + Part (b) An 8-bit biirectional -shifter is specie as: Inputs: x =(x ;x 9 ;x 8 ;x ;:::;x ;x, ;x, ;x, ), with x i f; g. s f; ; ; g fl; Rg f; g Output: y =(y ;y ;:::;y ;y ), with y j f; g. Function: y i = 8>< >: x i,s if ( = L) an ( =) x i+s if ( = R) an ( =) otherwise (9:) Let us assume that L =an R =. ach output is generate by an 8-input multiplexer as shown in Figure 9.9. The table for the control inputs c c c is: x i- x i- x i- x i x i+ x i+ x i+ MUX y i c c c Figure 9.9: Circuit for each output of the 8-bit biirectional shifter s c c c The values on the table are mappe into the following Kmaps, consiering that s is represente in binary coe:

18 8 Solutions Manual - Introuction to Digital Design - March, 999 s s s c s c s c s The switching expressions are: c = + s + s c = + s + s s + s s c = + s xercise 9.8 The moule is obtaine by renaming inputs an outputs of the shift register. For the right -shifter we have the specication: Inputs: x =(x n+;x n+;x n ;x n, ;:::;x ;x ), with x i f; g s f; ; ; g f; g Output: y =(y n, ;y n, ;:::;y ;y ), y i f; g Function: ( xj+s if = y j = (9:) otherwise An we woul like tohave a left -shifter, which is specie as: Inputs: w =(w n, ;w n, ;:::;w ;w ;w, ;w, ;w, ), with w i f; g s f; ; ; g f; g Output: z =(z n, ;z n, ;:::;z ;z ), z i f; g Function: ( wi,s if = z i = otherwise The mapping of the inputs is x i = w k with k = n,, i. Renaming the output also, we have (9:) y j = z t with t = n,, j. Replacing these values on quation 9. we obtain: z t =( xn,,t+s = w n,,(n,,t+s) = w t,s if = otherwise (9:)

19 Solutions Manual - Introuction to Digital Design - March, that correspons to a -left shifter. xercise 9.9 A n-bit p-shifter has (n +p) input bits an n output bits. It can shift right or left (irection input ) an the istance of shifting can vary from to p. The implementation of a -bit -shifter using four 8-bit -shifters is presente in Figure 9.. The circuit on the top is a -bit -shifter that shifts to the left only. The circuit on the bottom of the gure is a bi-irectional -bit -shifter. The input of the circuit was name i to i, an the output z to z. i to i i to i i to i 8 i to i shift inputs LFT istance from to s bit -shifter s bit -shifter s 8-bit -shifter s 8-bit -shifter z to z z to z z to z 8 z to z LFT -bit -shifter i to i i to i i to i 8 i to i shift inputs shift inputs LFT/RIGHT istance from to s bit -shifter s bit -shifter s bit -shifter s 8-bit -shifter z to z z to z z to z 8 z to z Bi-irectional -bit -shifter Figure 9.: xercise 9.9 xercise 9. Calling the output of stage w an of stage w then: w j = ( xj if s = x (j+)mo8 if s = which inicates that this stage rotates or position left epening on the value of s. Similarly, w j = ( wj if s = w (j+)mo8 if s = Finally,

20 8 Solutions Manual - Introuction to Digital Design - March, 999 y j = ( wj if s = w (j+)mo8 if s = an this correspons to rotating or positions. Consequently, the moule rotates left s =s +s + s positions with s. For example, if the input vector is (x ;x ; :::; x ) = the output vector, for a rotation of to the left is:. xercise 9. Design of Part (a) -bit right -shifter using -bit right shifter moules. The network is shown in Figure 9.. x x x x x x 9 x 8 x x x x x x x x ist right -shifter ist right -shifter ist right -shifter Figure 9.: -bit right -shifter Part (b) using k-bit right p-shifter moules we may implement a larger n-bit right p-shifter using: M = n k e moules of k-bit right p-shifter. The input vector of the n-bit shifter is: x =(x n+p,;x n+p,; :::; x n, ;x n, ; :::; x ;x ) ach k-bit shifter moule i receives the vector: x (i) =(x ik+p,; :::; x ik+;x ik ) The enable an istance control lines of all shifters are connecte together to from the control lines of the larger shifter. xercise 9. Consiering the network forme by the ecoer an the multiplexer we have that z = ( if (w; ; e) =(f;g;h) otherwise (9:) where w is the output of the rst multiplexer. An expression for this output is: w = a b c + bc + abc = ab + bc + a b c

21 Solutions Manual - Introuction to Digital Design - March, a b b c a b c w f g e h z Figure 9.: Network for xercise 9. The gate network that implements the network in Figure 9.8 of the textbook is shown in Figure 9.. The equality comparator that generates z is implemente using XOR an NOR gates (as propose in the hint). The gate network to generate w is implemente with AND an OR gates. xercise 9. The network in Figure 9.9 of the textbook has a serial line (w) between the MUX an DMUX that is escribe as: ( xi if i =a +b + c an w = = (9:) otherwise The outputs of the DMUX are specie as: Combining both equations we obtain: y i =( y i = ( w if i =a +b + c an = otherwise xi if i =a +b + c an = = otherwise (9:8) (9:9) So, y i is the same as x i or is zero. This circuit is useful to allow the sharing of the single line between Mux an Demux among all pairs of (input,output): (x ;y ), (x ;y )... an so on. It's use in communication lines to ivie the full capacity of the communication line among the many transmitters an receivers. ach pair can communicate without interference of the other pairs. xercise 9. From the network we obtain: Y = x y S + x y S + xy S + xy (S + S ) = x y (y y ) + x y y y + xy y y + xy (y y + y y ) = x y y + x y y + x y y y + xy y y + xy y Y = x y(s + S )+x y (S + S )+xys + xy (S + S ) = x y (y y + y y )+x y (y y + y y )+xy y y + xy (y y + y y ) = x y y y + x y y y + x y y + xy y y + xy y

22 8 Solutions Manual - Introuction to Digital Design - March, 999 Y = x y (S + S )+x y S + xy S + xy (S + S ) = x y (y y + y y )+x y y y + xy y y + xy (y y + y y ) = x y y + x y y y + xy y y + xy y z = (y y )y x =(y y + y y)y x = x(y y y + y y y ) From these expressions we following state transition an output table: State PS Input Number y y y x = x =,,,,,,,,,,,,,,,, NS (Y Y Y ),z To reuce the number of states we use the minimization proceure presente in Section. of the textbook. The rst partition is: Secon partition: Thir partition: # # x # # # x # # # # x No more new partitions! Stop. The reuce sequential system has only states. We rename the states as: Sate number State name, A, B, C, D an obtain the following state transition an output table:

23 Solutions Manual - Introuction to Digital Design - March, PS Input x = x = A A, B, B B, C, C C, D, D D, A, NS,z A state iagram for the system is shown in Figure 9. an correspons to a moulo- counter. / / A / B / / D / C / / Figure 9.: State igram for xercise 9. A better canonical implementation of this sequential circuit is shown in Figure 9. an it uses only two memory elements an some gates. The esign steps are not shown. Y y x x z Y y Figure 9.: Reesign of sequential system in xercise 9. xercise 9. From the circuit presente in the gure we can obtain the state iagram in Figure 9.. The binary ecoer connecte to the state register generates the signals S i, which is when the sequential system is at state i. The system outputs correspon to the state signals, that means, each output is active in one particular state. For this reason we use the output names as

24 8 Solutions Manual - Introuction to Digital Design - March, 999 state names to make the state iagram more meaningful. In each present state we ientify which input of the binary encoer is. This input etermines the next state. For example, the origin of arcs going into state S (check) are obtaine by consiering the input of the ncoer labele, which iss for input GO, S (always, no conition), an S (always). The state iagram shows the operation of a controller which starts to operate with a GO signal. During operation it monitors two variables: ist an count an issues movement control signals an counter control signals, until (ist ) an (count = ). GO Initial (ist ) an CLAR GO (count = ) COUNT check turn left (ist ) (count =) an ist > stop move count up Figure 9.: xercise 9. xercise 9.. The coewors of both systems are presente in the following table: n Coe A Coe B p =(n) mo q =(n) mo p p p q q q 8 9

25 Solutions Manual - Introuction to Digital Design - March, (a) the esign of an A-to-B converter using one 8-input multiplexer an one -input XOR gate is shown in Figure 9.. Observe that: q = p q = p q = p p an q is easily implemente using an 8-input multiplexer from the following function table: p p p p q p q p p q q MUX q p p p Figure 9.: Coe converter - xercise 9. (a) (b) the coe converter esigne using one -input ecoer an one -input encoer is shown in Figure 9..

26 88 Solutions Manual - Introuction to Digital Design - March, 999 p p p p ecoer encoer q q q q Figure 9.: Coe converter - xercise 9. (b)