EE-612: Lecture 25: CMOS Circuits: Part 2

Transcription

1 EE-612: Lecture 25: CMOS Circuits: Part 2 Mark Lundstrom Electrical and Computer Engineering Purdue University West Lafayette, IN USA Fall 2006 NCN Lundstrom EE-612 F06 1

2 Outline 1) Review 2) Speed (continued) 3) Power 4) Circuit performance Lundstrom EE-612 F06 2

3 CMOS inverter transfer characteristic S B noise margins V IN D D PMOS V OUT V OUT --> /2 NMOS /2 S B V IN --> Lundstrom EE-612 F06 3

4 importance of gain V out dv out = A υ = ( g mn + g mp )r ( on r op )> 1 dv in 2 A υ = 1 must have gain to have noise margins V in Lundstrom EE-612 F06 4

5 outline 1) Review 2) Speed (continued) 3) Power 4) Circuit performance Lundstrom EE-612 F06 5

6 CMOS inverter speed V IN S D D S V OUT + - τ = 1 2 R swn = k n I N (on) 2I N (on) + 2I P (on) ( ) τ = R swn + R swp 2 τ = R sw k n > 1 2 Lundstrom EE-612 F06 6

7 loaded propagation delay = C out + C L + FO C in C in V IN C out C wire Cin C in Lundstrom EE-612 F06 7

8 Miller C 0 C OV n+ n+ V D C OV + - feed forward 0 p-si 0 C M = 2C OV V c (t << 0) = ΔV c = 2 V c (t >> 0) =+ ΔQ c = ΔV c C OV = 2 C OV = C M Lundstrom EE-612 F06 8

9 on-current determines circuit speed τ = R sw R sw ~ / I D (ON) S I N D V OUT I N ( on) V IN D + S - V DSAT V DS 1) quasi-static assumption 2) simplified I D - V DS Lundstrom EE-612 F06 9

10 metrics for circuit speed K.K. Ng, et al., Effective On-Current of MOSFETs for Large-Signal Speed Consideration, IEDM, Dec., M.H. Na, et al., The Effective Drive Current in CMOS Inverters, IEDM, Dec., J. Deng and H.S.P. Wong, Metrics for Performance Benchmarking of Nanoscale Si and Carbon Nanotube FETs Including Device Nonidealities, IEEE Trans. Electron Dev., 53, pp , R. Venugopal, et al., Design of CMOS Transistors to Maximize Circuit FOM Using a Coupled Process and Mixed Mode Simulation Methodology, IEEE Electron Dev. Lett., 53, pp , Lundstrom EE-612 F06 10

11 outline 1) Review 2) Speed 3) Power 4) Circuit performance Lundstrom EE-612 F06 11

12 power V in (t) T V IN C 2 TOT 0 t Lundstrom EE-612 F06 12

13 discharge cycle V in (t) C 2 TOT E C (0) = 1 2 C 2 TOT E C (T /2)= 0 V in (t) T /2 P dynamic = ΔE T /2 = C V 2 TOT DD T 0 t 2 P dynamic = α f switching activity Lundstrom EE-612 F06 13

14 discharge through a resistor V in (t) - R V c (t) V C (t) = V c (0)e t / R t /τ = e P R (t) = V C 2 (t) R V in (t) 0 T /2 t P AVE = T /2 0 = 2 T P R (t)dt T /2 T /2 0 2 R 2 = f e 2t /τ dt Lundstrom EE-612 F06 14

15 charging cycle does it take power to put energy in the capacitor? V IN C 2 TOT Lundstrom EE-612 F06 15

16 charging cycle (ii) E C (0) = 0 V(t) V(t) T /2 + - V c (t) E C (T /2)= 1 2 C 2 TOT E B = T /2 0 T /2 0 E B = i(t)dt i(t) dt = Q 0 t 2 E B = Q = E diss = 1 2 C V 2 TOT DD Lundstrom EE-612 F06 16

17 charging cycle (iii) V(t) - R V c (t) i(t) = dv c dt V c (t) = it ( )R i(t) = R di dt V(t) 0 T /2 i(t) = i(0 + )e t /τ = ( R)e E B = T /2 0 i(t)dt 2 = t /τ t E diss = 1 2 C V 2 TOT DD Lundstrom EE-612 F06 17

18 adiabatic charging V(t) - R + dv i(t) = dt + - V c (t) P R = i 2 R = = T T 2 R V(t) E diss = T 0 P R dt = C 2 2 TOT T 2 RT 0 T t E diss = 2 R T Lundstrom EE-612 F06 18

19 outline 1) Review 2) Speed 3) Power 4) Circuit performance 5) CMOS circuit metrics Lundstrom EE-612 F06 19

20 device impact on circuit performace Question: Given a technology, how does circuit performance depend on transistor design (W, T OX,, etc.) Taur and Ning assume a 250nm technology and explore this question by Spice simulation (see pp ). Can we understand the major trends simply? Lundstrom EE-612 F06 20

21 effect of transistor W on delay ( ) τ = R + R swn swp 2 = R sw = C out + C wire + FO C in R sw = k I D (on) C out ~ W C in ~ W I(on) ~ W R sw ~1/W Lundstrom EE-612 F06 21

22 loaded vs. unloaded delay τ = R sw = R sw ( C out + FO C in + C wire ) i) unloaded: C in and C out dominate, ~ W --> τ independent of W ii) loaded: C L dominates, ~ independent of W --> τ ~1/ W Lundstrom EE-612 F06 22

23 effect of T OX on delay τ = R sw = R sw ( C out + FO C in + C L ) i) intrinsic delay (C L = 0) R sw = k / I D (ON) ~ T OX C in ~1/T OX τ int ~constant C out constant ii) loaded delay (C L > 0) τ loaded R sw C L τ loaded as T OX (see Fig of Taur and Ning) Lundstrom EE-612 F06 23

24 effect of L on delay τ = R sw = R sw ( C out + FO C in + C L ) R sw = k / I D (ON) I D (ON ) = WC OX υ(0) ( V GS V T ) as L R sw as L τ as L C in ~ L C out,c L constant (see Fig of Taur and Ning) Lundstrom EE-612 F06 24

25 effect of on delay τ = R sw = R sw ( C out + FO C in + C L ) R sw = k / I D (ON) I D (ON ) = WC OX υ(0) ( V GS V T ) R sw ~ ( V T ) R sw ~1 1 V T ( ) τ ~ 1 1 V T C out = ε Si W D ~1 + V bi Lundstrom EE-612 F06 25

26 delay vs. τ τ ~ 1 1 V T V T = 0.2 fixed V T V T (see Fig of Taur and Ning) I D (off) ~ e qv T /mk BT Lundstrom EE-612 F06 26

27 power-delay trade-off circuit speed: τ ~ ( V T ) f ~ ( 1 V T ) dynamic (switching) power: 2 P dynamic = α f 2 ~ ( ) 1 V T static (leakage) power: P static ~ I D (OFF) ~ e qv T /mk B T Lundstrom EE-612 F06 27

28 power-delay trade-off V T 2 P dynamic ~ decreasing active power LSP ( ) 1 V T speed ~ 1 V T increasing speed decreasing leakage power ( ) P static ~ e qv T /mk B T HP (see Fig of Taur and Ning) Lundstrom EE-612 F06 28

29 Outline 1) Review 2) Speed 3) Power 4) Circuit performance 5) CMOS circuit metrics Lundstrom EE-612 F06 29

30 key metrics 1) Switching energy: E S = 1 2 CV 2 DD 2) Switching delay: τ S = C I D (ON) 2 3) Dynamic power: P D = α fc 4) Energy-delay product: E S τ = 1 2 C 2 3 I D (on) Lundstrom EE-612 F06 30

31 the energy-delay metric Energy-delay product: E S τ = 1 2 C 2 3 I D (on) ~ 3 ( ) V T Minimum energy-delay product: ( E τ ) V S DD opt = 0 V = 1.5V DD T Lundstrom EE-612 F06 31

32 device metrics for 65 nm technology node 1) Switching energy: E S = 1 2 CV 2 DD 21 aj 2) Switching delay: τ S = C I D (ON) = 0.64 ps 2 3) Dynamic power: P D = α fc 4) Energy-delay product: E S τ = 1 2 C 2 3 I D (on) = J-s Lundstrom EE-612 F06 32

33 circuit performance (high-speed logic) Typical power dissipation of a logic chip: Dissipation of logic core: 100 W 20 W 2 C P core = N S core 2 C S 10 ff/node fα = 10 7 C S 12 2 ( ) 10 1 Average switching energy: E S C V 2 S DD 2 = 6,000 aj Energy-delay product: E S τ J-s Lundstrom EE-612 F06 33

34 from device to circuit device circuit increase delay: switching energy: energydelay: 0.64 ps 250 ps ~ aj 6000 aj ~300 ~ J-s ~ J-s ~100,000 Lundstrom EE-612 F06 34

35 Outline 1) Review 2) Speed 3) Power 4) Circuit performance 5) CMOS circuit metrics Lundstrom EE-612 F06 35

36 conclusions / questions 1) Device metrics aren t enough; the circuit is critical. 2) How close is CMOS to fundamental limits? Lundstrom EE-612 F06 36