Equalization/Compensation of Transmission Media. Channel (copper or fiber)

Transcription

1 Equalization/Compensation of Transmission Media Channel (copper or fiber) 1

2 Optical Receiver Block Diagram O E TIA LA EQ CDR DMUX -18 dbm 10 µa 10 mv p-p 400 mv p-p 2

3 Copper Cable Model Copper Cable 4-foot cable H( ω) e Lα ω 15-foot cable Where: L is the cable length a is a cable-dependent characteristic 2

4 Effect of Copper on Broadband Data waveform eye diagram 3

5 Adaptive Analog Equalizer for Copper Implemented in Jazz Semiconductor SiGe BiCMOS process: 120 GHz f T npn 0.35 µm CMOS 4

6 Equalizer Block Diagram 5

7 Analog Equalizer Concept (1) Simple linear circuit (normalized to 1Hz): 1 V V 1 2 V s C V 1 α V 1 ( 1 α) V 2 1 simple channel model bandpass filter combined flat response + peaked response 6

8 Analog Equalizer Concept (2) 1 V 1 V 2 V s C V 1 α V 1 ( 1 α) V 2 1 V 1 V 2 7

9 Analog Equalizer Concept (3) Equalized output pulses: Rise time = voltage swing/slew rate V 3 Rise time nearly constant over different channels! 8

10 Feedforward Path V out 9

11 Equalizer Frequency Response V eq V in (db) V control f (Hz) 10

12 ISI & Transition Time V FFE t eq = 45ps PW = 108ps t eq = 60ps PW = 100ps t eq = 75ps PW = 86ps t (ns) Simulations indicate that ISI correlates strongly with FFE transition time t eq. Optimum t eq is observed to be 60 ps. Nonlinearities affect pulse shape, but not location of zero crossings. 11

13 Slicer Restores full logic levels Exhibits controlled transition time 12

14 Feedback Path 13

15 Transition Time Detector DC characteristic: V S V + V - V S I SS C SS Transient Characteristic: V + V (b) (a) V + V Rectification & filtering done in a single stage. V S (b) (a) 14 t

16 Integrator H(s) = A sτ int A 0 sτ int A 0 = g ( m 1 r o1 r ) o2 τ int = C L g m 1 15

17 Detector + Integrator From FFE t FFE From Slicer t slicer = 60ps V control (mv) FFE transition Time t FFE slope detector slope detector ps 75ps 0 60ps _ + V control t (ns) 45ps 15ps 16

18 System Analysis t slicer detector K d + _ V control integrator H(s) feedforward equalizer K eq t eq detector K d t t eq slicer H( s) KdK = 1+ K K 1 sτ int d eq H( s) eq H( s) t t eq slicer = 1+ s τ int 1 K d K eq K eq = 1.5 ps/mv K d = 2.5 mv/ps τ int = 75ns τ adapt = τ int K d K eq = 20ns 17

19 Measurement Setup EQ inputs Die under test 2 31 PRBS signal applied to cable EQ outputs 18

20 Measured Eye Diagrams EQ input EQ output 4-foot RU256 cable (-5 db 5 GHz) 4.0 ps rms jitter 15-foot RU256 cable (-15 db 5 GHz) 3.9 ps rms jitter 19

21 Summary of Measured Performance Supply voltage 3.3 V Power Dissipation Die Size 350 mw (155 mw not including output driver) 0.81mm X 0.87mm Output Swing 490 mv single-ended p-p Random Jitter 4.0 ps rms (4-foot cable) 3.9 ps rms (15-foot cable) Presented at ISSCC Feb

22 Equalization vs. Compensation Equalization is accomplished by inverting the transfer function of the channel. Compensation is accomplished only by canceling the ISI at each unit interval. Electronic Dispersion Compensation (EDC) refers to the electronics that accomplishes compensation of copper or optical transmission media. EDC is becoming especially critical as bit rates increase on legacy equipment (e.g., backplane, optical connectors, optical fiber). 21

23 Pre-Cursor/Post-Cursor ISI Input pulse (no ISI): 0 T Output pulse: pre-cursor ISI cursor post-cursor ISI 0 T 22

24 Feedforward Equalization (FFE) Idea: To cancel ISI, subtract a weighted & delayed version of the pulse: output pulse delayed by T: d -1 output pulse: d 0 # X d & 1 % ( $ ' d 0 Result with 0 pre-cursor ISI: 23

25 Feedforward Equalization (2) D in (t) T D in (t T) Time domain: + a 1 _ Σ D out (t) D out (t) = D in (t) a 1 D in (t T) a 1 = d 1 d 0 Frequency domain: 1+ a 1 2 H(s) = 1 a 1 e st H( jω) = 1 a 1 e jωt ( ) = 1 a 1 cosωt j sinωt 1 a 1 H( jω) 2 = (1+ a 1 2 ) 2a 1 cosωt π T ω 24

26 Feedforward Equalization (3) N-tap FFE structure: D in (t) T T T a 0 a 1 a 2 a n Σ D out (t) FFE can cancel both pre- and post-cursor distortion. 25

27 Feedforward Equalization (4) 3-tap summing circuit: R R negative coefficient D in+ (k) _ V out + D in (k) D in+ (k 1) D in (k 1) D in+ (k 2) D in (k 2) V 0 V 1 V 2 I SS Coefficients set by g m of each differential pair. 26

28 Feedforward Equalization (5) Fractional spacing: π T ω 1-tap T-spaced FFE frequency response 5-tap T-spaced FFE eye diagram 2π T 1-tap T/2-spaced FFE frequency response ω 5-tap T/2-spaced FFE eye diagram 27

29 Adaptation (1) Assume original sequence D in (k) is known. Define error signal e(k) as: ^ e(k) D out (k) D out (k) ^ where D out (k) is an appropriately delayed version of D in (k). Steepest Descent Algorithm: e 2 optimum setting Set Δa i a 2 a 1 = µ de2 da i step size Algorithm moves coefficients in direction of decreasing mean-square error. Step size µ should be made sufficiently small to guarantee convergence. Requires knowledge of properties of mean-square error; usually not available. 28

30 Adaptation (2) Least mean-square (LMS) algorithm: Set Δa i = µ d [ e2 (k)] da i FFE output signal: D out (k) = a 0 D in (k) + a 1 D in (k 1) + + a n D in (k n) [ ] 2 e 2 ^ (k) = D out (k) D out (k) [ ] da i d e 2 (k) ( ) dd out = 2 D ^ out D out = 2 e(k) D in (k i) da i Δa i = 2µ e(k) D in (k i) Analog version of LMS: a i (t) = 1 τ e(t) D in (t it)dt both signals are available on chip. 29

31 Adaptation (3) Types of adaptation: 1. Training Sequence A training sequence with known properties is sent through the channel + equalizer. The equalizer output is compared to the original sequence and an error signal is generated. 2. Blind Adapation Adaptation is continually performed while system is running. Only limited properties of the signal are known. An error signal must somehow be generated without having the original sequence. 30

32 Adaptation (4) Generation of error signal: D in FFE D out ^ D out _ Σ + e Slicer restores logic levels and opens eye vertically. Bit sequences at slicer input & input are identical. Slicer has no effect on placement of zero crossing. Slicer can be realized using CML buffers with sufficient gain and speed. 31

33 Decision Feedback Equalization (DFE) FFE structure: D in (t) T T T a 0 a 1 a 2 a n Σ D out (t) Noise applied to FFE input will be retained (perhaps filtered) at the output. DFE structure: D in (t) + Σ D out (t) b m b 2 b 1 T T T 32

34 Decision Feedback Equalization (2) D in (t) Σ D out (t) b m b 2 b 1 T T T Slicer is embedded in the structure; D out is a digital signal. Delay elements are digital -- commonly realized by DFFs. Use of slicer suppresses input noise. Cancels post-cursor distortion only. 33

35 Decision Feedback Equalization (3) D in (t) + Σ D out (t) 1-tap example: D in (k) 2/3 post-cursor distortion 1/3 b m b 2 b 1 consistent with D out (k) (desired) 1 1 T T T D out (k 1) Tap weights provide a look-up table, canceling post-cursor distortion based on last m bits of output sequence. DFE can sometimes latch up with wrong tap weights during adaptation. D in (k) 1 3 D out (k 1) 2/3 b 1 =

36 FFE + DFE D in (t) T T T a 0 a 1 a 2 a n Σ + Σ D out (t) Combined FFE and DFE can be used to cancel both pre- and post-cursor distortion with low noise. b m b 2 b 1 T T T 35

37 Front-End Circuits for DSP-Based Receivers from channel V in V PGA A ADC D out [1:n] ADC requires strict control over its input amplitude V A. V C AGC Programmable Gain Amplifier (PGA): V A (t) = G(V C ) V in (t) where # G(V C ) = V 1 exp V & C % ( $ ' V 2 Automatic Gain Control Linear in db gain characteristic gives settling time independent of input amplitude. 36

38 PGA Design 1. Differential Pair: 2. Source Degeneration: 3. Op-Amp with Feedback: I out- V in+ I out+ V in- I out- V in+ I out+ V in- + V_ in R S R S R f + V_ out I SS 2R S + V C _ R f For biasing in weak inversion: I SS I out = g m V in 2nV T % I SS = I D0 exp V V ( C T ' * & nv T ) I out = g m 1+ g m R S V in V in R S for g m R S >> 1 V out = R f R S V in R S varied with constant db per step. 37

39 PGA Example (1) C.-C. Hsu, J.-T. Wu, A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier, JSSC, Oct. 2003, pp V out = R f R S V in Realization of R S : R S1 = 420 R S1 + R S2 = 529 R S1 + R S2 + R S3 = 666 R S1 + R S2 +!+ R S10 = db steps 38

40 PGA Example (2) J. Cao, et al., A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s links over backplane and multimode fiber, ISSC 2009, pp A v = g m R = N µ n C ox W L I O R gain of single diff. pair where N = number of diff. pairs turned on 39

41 Track & Hold Circuit The T/H circuit is comprised of two switch-capacitor stages and an amplifier which provides gain and isolation. Dummy switches are used to cancel channel charge injection and achieve better linearity. 40

42 Simulation Results T/H differential output for f in = 1.5 GHz and f s =10 GS/sec 41

43 High-speed Comparator High-Level Clocking: Improves isolation between the input and output, reducing kickback from output. Cascoding of the clock switches reduces the Miller effect of the input transistors. Reduced headroom 42

44 Comparator/Latch Results (1) 43

45 Metastable Behavior (1) Comp./Latch output Metastable event T/H output What is the probability of this error occurring? 44

46 Metastable Behavior (2) For v d v 1 v 2 : C t R + v 1 + v 2 R v d (t) C t C t dv d dt = v d R + g m v d % v d (t) = v d (0) exp' & τ m g m C t t τ m ( * ) g m R g m = 4.2 ms R = 400 Ω C t = 36 ff τ m = 30 ps t 45

47 V out (digital) Metastable Behavior (3) V dec -ε +ε +V dec V in (analog) 2ε 2V dec V LSB Error probability: Including comparator gain: P error = 2ε P error = V LSB 2ε A comp V LSB V dec = minimum detectable logic level ε = minimum input at t = 0 so that output level is V dec at t = T/2 46

48 Metastable Behavior (4) v d (t) Recall: $ v d (t) = v d (0) exp& % v d (T c 2) V dec t τ m ' ) ( For error-free operation after half-clock period: ' V dec = ε exp T * c ), ( 2τ m + ' ε = V dec exp T * c ), ( 2τ m + τ m = 23 ps τ m = 30 ps t Error probability: P error = = 2ε A comp V LSB 2V & dec exp T ) c ( + A comp V LSB ' 2τ m * 47

49 Reducing Metastability Errors Additional high-speed latches following the comparator/latch stage reduces probability of metastable events at the output. Latch output 48