EE539: Analog Integrated Circuit Design

Transcription

1 Introduction Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, , India 1 Jan. 2008

2 Outline Sensor(s) Digital Processing Actuator(s) Continuous-time Continuous-amplitude... DSP Discrete -time Discrete -amplitude Interface Electronics (Signal Conditioning) (A-D and D-A Conversion) Continuous-time Continuous-amplitude

3 Analog circuits in modern systems on VLSI chips Analog to digital conversion Digital to analog conversion Amplification Signal processing circuits at high frequencies Power management-voltage references, voltage regulators Oscillators The last two are found even on many digital ICs

4 Image sensor[isscc 2004] Chip Micrograph Voltage Regulator 703 x 499 pixels (VGA format) Column CDS circuits Timing Generator I/O circuit 10b pipelined ADC Chip size: 4.74mm x 6.34mm

5 Wireless LAN transceiver[isscc 2004]

6 DRAM[ISSCC 2004] 64 I/Os ADDRESSES AND CONTROL BANK 3 BANK 2 64 I/Os ROW DECODERS DATA LINES BANK 1 COLUMN DECODERS 1088 SENSE AMPS 512K ARRAY BANK 0 VPP PUMP

7 Analog IC design in India Many companies starting analog centers Multinationals-TI, National, ST, ADI etc. Indian start ups-cosmic, Karmic, Sankalp etc. Big demand for skilled designers Interesting and profitable activity

8 Course goals Learn to design negative feedback amplifiers on CMOS ICs Negative feedback for controlling the output Amplifiers, voltage references, voltage regulators, biasing

9 Course prerequisites Circuit analysis Small and large signal analysis Laplace transforms, frequency response, Bode plots Differential equations Opamp circuits Basic transistor models and circuits

10 Course contents-introduction/review Circuit analysis, laplace transforms, differential equations Amplifiers using negative feedback Negative feedback circuits using opamps

11 Course contents-amplifiers on ICs Components available in CMOS integrated circuit (IC) processes Device models-dc small signal, dc large signal, ac small signal, mismatch, noise Basic single transistor amplifier stages Transistor biasing, compound amplifier stages Differential amplifiers Fully differential amplifiers and common mode feedback

12 Course contents-design of opamps Single stage opamp Folded, telescopic cascode opamps Two stage opamp Fully differential opamps and common mode feedback Applications: Bandgap reference, constant g m bias generation

13 Design versus Analysis Design: Create something that doesn t yet exist Analysis: Analyze something that exists

14 To be able to design Knowing analysis is necessary, not sufficient Multiple ways of looking at building blocks Trial and error approaches Intuitive thinking/understanding Curiosity Open mind Thoroughness

15 Intuition Intuitive thinking is not sloppy thinking! Relate problems to other problems already solved Use boundary conditions, dimension checks etc. Build your intuition Solve many problems Think about why the answer is what it is Come up with the form of the solution before applying full blown analysis

16 Circuit analysis Nodal analysis-kirchoff s Current Law (KCL) at each node Solve N simultaneous equations for an N node circuit Mesh analysis-kirchoff s Voltage Law (KVL) around each loop Solve M simultaneous equations for a circuit with M independent loops

17 Nodal analysis i 11 (v) + i 12 (v) i 1N (v) = i 1 i 21 (v) + i 22 (v) i 2N (v) = i 2 i N1 (v) + i N2 (v) i NN (v) = i N. i kl : Current in the branch between nodes k and l i kk : Current in the branch between node k and ground v k : Voltage at node k; v = [v 1 v 2... v N ] T i k : Current source into node k i kl can be a nonlinear function of v

18 Nodal analysis Linear circuits g 11 v 1 + g 12 v g 1N v N = i 1 g 21 v 1 + g 22 v g 2N v N = i 2. g N1 v 1 + g N2 v g NN v N = i N g kl : Conductance between nodes k and l g kk : Conductance between node k and ground v k : Voltage at node k i k : Current source into node k

19 Nodal analysis Independent voltage source. g k1 v 1 + g k2 v g kn v N = i k node k. v k = V o node k Ideal voltage source V o connected to node k

20 Nodal analysis Controlled voltage source. g k1 v 1 + g k2 v g kn v N = i k node k. v k kv l = 0 node k Voltage controlled voltage source v k = kv l driving node k

21 Nodal analysis Controlled voltage source g k1 v 1 + g k2 v g kl v l g kn v N = i k node k g k1 v 1 + g k2 v v k g kn v N R m = i k node k g l1 v 1 + g l2 v g lk v k g ln v N = i l node l g l1 v 1 + g l2 v v k R m g ln v N = i l node l Current controlled voltage source v k = R m i kl driving node k

22 Nodal analysis Controlled current source g k1 v 1 + g k2 v g kl v l g kn v N = i k + g m v l g k1 v 1 + g k2 v g kl v l g m v l g kn v N = i k Current controlled voltage source i 0 = g m v l driving node k

23 Nodal analysis Ideal opamp. g m1 v 1 + g m2 v g mn v N = i m node m. v k v l = 0 node m Ideal opamp with input terminals at nodes k, l and output at node m

24 Nodal analysis solution g 11 g g 1N v 1 g 21 g g 2N v 2.. = g N1 g N2... g NN v N Gv = i i 1 i 2. i N v = G 1 i g kl : Conductance between nodes k and l g kk : Conductance between node k and ground v k : Voltage at node k i k : Current source into node k Modified terms for voltage sources or controlled sources Matrix inversion yields the solution

25 Nodal analysis solution v k = g 11 g i 1... g 1N g 21 g i 2... g 2N. g N1 g N2... i N... g NN g 11 g g 1k... g 1N g 21 g g 2k... g 2N. g N1 g N2... g Nk... g NN Cramer s rule can be used for matrix inversion

26 Circuits with capacitors and inductors Y 11 (s)y 12 (s)... Y 1N (s) Y 21 (s)y 22 (s)... Y 2N (s). Y N1 (s)y N2 (s)... Y NN (s) V 1 (s) V 2 (s). = V N (s) Y(s)V (s) = I(s) I 1 (s) I 2 (s). I N (s) V (s) = Y 1 I(s) Conductances g kl replaced by admittances Y kl (s) Roots of the determinant of Y(s) are system poles

27 Laplace transform analysis for linear systems Input Output X(s) H(s)X(s) e st H(s)e st X(jω) H(jω)X(jω) e jωt H(jω)e jωt cos(ωt) H(jω) cos (ωt + H(jω)) (Steady state solution) Linear time invariant system described by its transfer function H(s) H(s) is the laplace transform of the impulse response s = jω represents a sinusoidal frequency ω

28 Laplace transform analysis for linear systems Transfer function H(s) (no poles at the origin) H(s) = A dc 1 + b 1 s + b 2 s b M s M 1 + b 1 s + b 2 s b N s N = A dc M k=1 1 + s/z k N k=1 1 + s/p k Single pole at the origin H(s) = ω u s M k=1 1 + s/z k N k=2 1 + s/p k All poles p k must be in the left half plane for stability

29 Frequency and time domain analyses Frequency domain Algebraic equations-easier solutions Only for linear systems Time domain Differential equations-more difficult to solve Can be used for nonlinear systems as well Piecewise linear systems occur quite frequently (e.g. saturation)

30 Bode plots Sinusoidal steady state response characterized by H(jω), H(jω) Bode plot: Plot of 20 log H(jω), H(jω) versus log ω approximated by straight line segments Good approximation for real poles and zeros

31 Simulators Very power tools, indispensable for complex calculations, but GIGO! Matlab: System level analysis (Frequency response, pole-zero, transfer functions) Spice: Circuit analysis Maxima: Symbolic analysis

32 References Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, August Hayt and Kemmerly, Engineering Circuit Analysis, McGraw Hill, 6/e. B. P. Lathi, Linear Systems and Signals, Oxford University Press, 2 edition, Sergio Franco, Design with operational amplifiers and analog ICs, Tata McGraw Hill. H. Takahashi et al., A 3.9 µm pixel pitch VGA format 10b digital image sensor with 1.5-transistor/pixel, IEEE International Solid-State Circuits Conference, vol. XVII, pp , February M. Zargari et al., A single-chip dual-band tri-mode CMOS transceiver for IEEE a/b/g WLAN, IEEE International Solid-State Circuits Conference, vol. XVII, pp , February K. Hardee et al. A 0.6V 205MHz 19.5ns trc 16Mb embedded DRAM, IEEE International Solid-State Circuits Conference, vol. XVII, pp , February 2004.